EP20K200EFC484-1 vs EP20K200EFC484-1N Comparison
Detailed side-by-side comparison of EP20K200EFC484-1 by Altera and EP20K200EFC484-1N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K200EFC484-1 - APEX 20KE FPGA 200K Gates 484-BGA | Altera
EP20K200EFC484-1 β Last Time Buy
Specification Comparison
| Parameter | EP20K200EFC484-1 | EP20K200EFC484-1N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $68.40 | $290.00 |
| Family | APEX 20KE | APEX-20KE |
| Logic Elements / Cells | 8320 | β |
| System Gates | 200000 | 200,000 |
| Embedded Memory (Bits) | 106496 | β |
| Maximum User I/O | 376 | 376 |
| Number of PLLs | 4 | β |
| Core Voltage | 1.8 V | β |
| Process Technology | 0.22 Β΅m CMOS | 0.22 Β΅m CMOS |
| Package | 484-BGA (FineLine BGA) | 484-ball FineLine BGA (23 mm Γ 23 mm) |
| Package Ball Count | 484 | β |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| Operating Temperature | -40 Β°C to +85 Β°C (industrial, inferred from grade code) | 0 Β°C to +85 Β°C (commercial) |
| I/O Standard Support | LVDS, PCI, LVTTL, LVCMOS, SSTL, HSTL | β |
| Programming Interface | IEEE 1149.1 JTAG, passive serial, passive parallel | IEEE 1149.1 JTAG |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance] |
| MSL Level | [DATA_NEEDED: MSL moisture sensitivity level] | [DATA_NEEDED: MSL rating] |
| Logic Elements | β | 8,320 |
| Embedded RAM Bits | β | 106,496 |
| Core Voltage (VCCINT) | β | 1.8 V (1.71 V to 1.89 V) |
| I/O Voltage (VCCIO) | β | [DATA_NEEDED: VCCIO range] |
| Maximum Internal Frequency | β | 367 MHz |
| Propagation Delay | β | 2.5 ns (per digchip reference) |
| Speed Grade | β | -1 |