EP20K200EFC484-1 vs EP20K200EFC484-1N Comparación
Comparación detallada lado a lado de EP20K200EFC484-1 por Altera y EP20K200EFC484-1N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EP20K200EFC484-1 - APEX 20KE FPGA 200K Gates 484-BGA | Altera
EP20K200EFC484-1 ⚠ Última compra
Comparación de especificaciones
| Parámetro | EP20K200EFC484-1 | EP20K200EFC484-1N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $68,40 | $290,00 |
| Family | APEX 20KE | APEX-20KE |
| Logic Elements / Cells | 8320 | — |
| System Gates | 200000 | 200,000 |
| Embedded Memory (Bits) | 106496 | — |
| Maximum User I/O | 376 | 376 |
| Number of PLLs | 4 | — |
| Core Voltage | 1.8 V | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Encapsulado | 484-BGA (FineLine BGA) | 484-ball FineLine BGA (23 mm × 23 mm) |
| Package Ball Count | 484 | — |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Temperatura de funcionamiento | -40 °C to +85 °C (industrial, inferred from grade code) | 0 °C to +85 °C (commercial) |
| I/O Standard Support | LVDS, PCI, LVTTL, LVCMOS, SSTL, HSTL | — |
| Programming Interface | IEEE 1149.1 JTAG, passive serial, passive parallel | IEEE 1149.1 JTAG |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance] |
| Nivel MSL | [DATA_NEEDED: MSL moisture sensitivity level] | [DATA_NEEDED: MSL rating] |
| Logic Elements | — | 8,320 |
| Embedded RAM Bits | — | 106,496 |
| Core Voltage (VCCINT) | — | 1.8 V (1.71 V to 1.89 V) |
| I/O Voltage (VCCIO) | — | [DATA_NEEDED: VCCIO range] |
| Maximum Internal Frequency | — | 367 MHz |
| Propagation Delay | — | 2.5 ns (per digchip reference) |
| Speed Grade | — | -1 |