EP20K200EQC208-3N vs EP20K200EQC208-3 Comparison
Detailed side-by-side comparison of EP20K200EQC208-3N by Intel and EP20K200EQC208-3 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K200EQC208-3
EP20K200EQC208-3 - APEX 20KE 200K Gate FPGA, 208-PQFP | Intel
EP20K200EQC208-3 ObsoleteSpecification Comparison
| Parameter | EP20K200EQC208-3N | EP20K200EQC208-3 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $65.00 |
| Device Type | Field Programmable Gate Array (FPGA) | β |
| Product Family | APEX 20K | β |
| Logic Family | CMOS | β |
| Gate Capacity | 200K gates | β |
| Logic Cells | 8,320 cells | β |
| Macro Count | 832 macros | β |
| User I/O Count | 136 I/Os | β |
| Maximum Operating Frequency | 189 MHz | β |
| Propagation Delay | 2.5 ns | β |
| Supply Voltage | 1.8 V | β |
| Alternate Supply Listing | 2.5 V | β |
| Package | 208-pin PQFP | 208-BFQFP / PQFP208 (Plastic Quad Flat Pack, gull-wing) |
| Alternate Package Listing | 356-ball BGA | β |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0 C to 85 C | β |
| Configuration | MultiCore programmable architecture | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| REACH Status | [DATA_NEEDED: REACH status] | β |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | β |
| Family | β | APEX 20KE |
| Series | β | APEX 20K (enhanced "E" variant) |
| Product Type | β | FPGA (Field Programmable Gate Array), SRAM-based, in-system programmable |
| System Gates (typical) | β | 200,000 |
| Logic Elements (LEs) | β | 8,320 |
| Embedded RAM Bits | β | 106,496 |
| Maximum User I/O | β | 136 |
| Speed Grade | β | -3 |
| Core Supply Voltage (VCCINT) | β | 2.5 V (typical, APEX 20KE generation) |
| I/O Supply Voltage (VCCIO) | β | MultiVolt, 1.8 V / 2.5 V / 3.3 V / 5 V compatible |
| Terminal Pitch | β | 0.5 mm |
| Technology | β | CMOS, SRAM configuration cell |
| Configuration Mode | β | Fast Passive Parallel (FPP), Passive Serial (PS), JTAG (IEEE 1149.1) |
| Embedded Array Blocks (EABs) | β | Yes (dual-port RAM/ROM, up to 16-bit wide) |
| MultiVolt I/O Support | β | Yes |
| LVDS Support | β | True-LVDS (enhanced "E" variant feature) |
| Moisture Sensitivity Level (MSL) | β | 3 (168 Hours) |
| Operating Temperature (Commercial) | β | 0 Β°C to 85 Β°C |