EP20K200EQC208-3N vs EP20K200EQC208-3 Comparaison
Comparaison détaillée côte à côte de EP20K200EQC208-3N par Intel et EP20K200EQC208-3 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K200EQC208-3N | EP20K200EQC208-3 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $65,00 |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Product Family | APEX 20K | — |
| Logic Family | CMOS | — |
| Gate Capacity | 200K gates | — |
| Logic Cells | 8,320 cells | — |
| Macro Count | 832 macros | — |
| User I/O Count | 136 I/Os | — |
| Maximum Operating Frequency | 189 MHz | — |
| Propagation Delay | 2.5 ns | — |
| Tension d'alimentation | 1.8 V | — |
| Alternate Supply Listing | 2.5 V | — |
| Boîtier | 208-pin PQFP | 208-BFQFP / PQFP208 (Plastic Quad Flat Pack, gull-wing) |
| Alternate Package Listing | 356-ball BGA | — |
| Type de montage | Surface Mount | Surface Mount |
| Température de fonctionnement | 0 C to 85 C | — |
| Configuration | MultiCore programmable architecture | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Family | — | APEX 20KE |
| Series | — | APEX 20K (enhanced "E" variant) |
| Product Type | — | FPGA (Field Programmable Gate Array), SRAM-based, in-system programmable |
| System Gates (typical) | — | 200,000 |
| Logic Elements (LEs) | — | 8,320 |
| Embedded RAM Bits | — | 106,496 |
| Maximum User I/O | — | 136 |
| Speed Grade | — | -3 |
| Core Supply Voltage (VCCINT) | — | 2.5 V (typical, APEX 20KE generation) |
| I/O Supply Voltage (VCCIO) | — | MultiVolt, 1.8 V / 2.5 V / 3.3 V / 5 V compatible |
| Terminal Pitch | — | 0.5 mm |
| Technology | — | CMOS, SRAM configuration cell |
| Configuration Mode | — | Fast Passive Parallel (FPP), Passive Serial (PS), JTAG (IEEE 1149.1) |
| Embedded Array Blocks (EABs) | — | Yes (dual-port RAM/ROM, up to 16-bit wide) |
| MultiVolt I/O Support | — | Yes |
| LVDS Support | — | True-LVDS (enhanced "E" variant feature) |
| Niveau de sensibilité à l'humidité (MSL) | — | 3 (168 Hours) |
| Operating Temperature (Commercial) | — | 0 °C to 85 °C |