EP20K400BC652-2AA vs EP20K400BI652-2 Comparison
Detailed side-by-side comparison of EP20K400BC652-2AA by Intel and EP20K400BI652-2 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400BC652-2AA | EP20K400BI652-2 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $108.40 |
| Product Type | Field-programmable gate array (FPGA) | β |
| Series | APEX-20K | APEX-20KC |
| Number of LABs/CLBs | 1664 | β |
| Number of Logic Elements/Cells | 16640 | β |
| Total RAM Bits | 212992 bit | 212992 |
| Number of I/O | 502 | β |
| Number of Gates | 1052000 | β |
| Supply Voltage | 2.375 V to 2.625 V | β |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0 Β°C to 85 Β°C (TJ) | [DATA_NEEDED: operating temperature grade] |
| Package | 652-BGA | 652-BGA (45 x 45 mm) |
| Supplier Device Package | 652-BGA (45x45) [DATA_NEEDED: target-device package dimensions] | β |
| Part Status | Obsolete | β |
| Configuration Memory Technology | [DATA_NEEDED: configuration memory technology] | β |
| Maximum User I/O Frequency | [DATA_NEEDED: maximum user I/O frequency] | β |
| Core Logic Voltage | [DATA_NEEDED: core logic voltage] | β |
| Typical Supply Current | [DATA_NEEDED: typical supply current] | β |
| RoHS Status | unknown | [DATA_NEEDED: RoHS compliance] |
| REACH Status | unknown | β |
| AEC-Q100 Qualification | unknown | β |
| Family | β | APEX 20K |
| Logic Elements / Cells | β | 16640 |
| System Gates | β | 400000 |
| Number of Logic Array Blocks (LABs) | β | 502 |
| User I/O Count | β | 502 (max per family) |
| Number of I/O Banks | β | 8 |
| Core Voltage | β | 1.71 V to 1.89 V |
| I/O Voltage Reference | β | 2.5 V (LVDS support) |
| Maximum Frequency | β | 200 MHz |
| Process Technology | β | 0.22 Β΅m CMOS |
| Pin-to-Pin Delay (Tpd) | β | 3.1 ns |