EP20K400CB652I9 vs EP20K400CB652C9ES Comparison

Detailed side-by-side comparison of EP20K400CB652I9 by Altera and EP20K400CB652C9ES by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K400CB652I9 EP20K400CB652C9ES
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $99.50 $195.00
Family APEX 20KC APEX 20KC
Logic Elements 16,640 cells β€”
System Gates 400,000 β€”
Maximum User I/O 488 β€”
Embedded Memory Bits 212,992 bits β€”
Embedded System Blocks (ESBs) 104 β€”
Process Technology 0.15 um CMOS 0.15 Β΅m CMOS
Core Voltage 1.8 V 1.8 V
Maximum Frequency 250 MHz β€”
Package 652-pin LBGA (CB) β€”
Maximum Seated Height 1.63 mm β€”
Operating Temperature -40C to +85C (industrial, 'I' grade) β€”
Speed Grade -9 β€”
Total Terminals 652 β€”
RoHS Status [DATA_NEEDED: RoHS compliance verification] [DATA_NEEDED: RoHS status]
Series β€” APEX 20KC
Logic Elements / Cells β€” 16640
Total System Gates β€” 400000
Embedded Memory (Bits) β€” 212992
Number of User I/O β€” 488
Number of LABs/CLBs β€” [DATA_NEEDED: LAB count]
Number of Logic Array Blocks β€” 1040
Maximum Operating Frequency β€” 250 MHz
Operating Temperature Range β€” 0Β°C to +85Β°C (Commercial)
Mounting Type β€” Surface Mount
Package / Case β€” 652-BGA
MSL Level β€” 3 (168 Hours)
Packaging β€” Tray
Programmability Type β€” In-system programmable (SRAM-based)
I/O Standards Supported β€” LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL
JTAG (IEEE 1149.1) β€” Yes
PLL β€” Yes (4-phase)

Datasheets & Resources

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