EP20K400CB652I9 vs EP20K400CB652C9ES 对比

详细并排对比 EP20K400CB652I9 出自 Altera 和 EP20K400CB652C9ES 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400CB652I9 EP20K400CB652C9ES
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 不推荐新设计
库存状态 有库存 有库存
单价(USD) $99.50 $195.00
Family APEX 20KC APEX 20KC
Logic Elements 16,640 cells —
System Gates 400,000 —
Maximum User I/O 488 —
Embedded Memory Bits 212,992 bits —
Embedded System Blocks (ESBs) 104 —
Process Technology 0.15 um CMOS 0.15 µm CMOS
Core Voltage 1.8 V 1.8 V
Maximum Frequency 250 MHz —
封装 652-pin LBGA (CB) —
Maximum Seated Height 1.63 mm —
工作温度 -40C to +85C (industrial, 'I' grade) —
Speed Grade -9 —
Total Terminals 652 —
RoHS 状态 [DATA_NEEDED: RoHS compliance verification] [DATA_NEEDED: RoHS status]
Series — APEX 20KC
Logic Elements / Cells — 16640
Total System Gates — 400000
Embedded Memory (Bits) — 212992
Number of User I/O — 488
Number of LABs/CLBs — [DATA_NEEDED: LAB count]
Number of Logic Array Blocks — 1040
Maximum Operating Frequency — 250 MHz
工作温度范围 — 0°C to +85°C (Commercial)
安装类型 — Surface Mount
封装 / 外壳 — 652-BGA
MSL 等级 — 3 (168 Hours)
Packaging — Tray
Programmability Type — In-system programmable (SRAM-based)
I/O Standards Supported — LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL
JTAG (IEEE 1149.1) — Yes
PLL — Yes (4-phase)

数据手册与资源

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