EP20K400CF672C7ES vs EP20K400CF672C8ES Comparison
Detailed side-by-side comparison of EP20K400CF672C7ES by Altera and EP20K400CF672C8ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400CF672C7ES | EP20K400CF672C8ES |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $152.00 | $158.40 |
| Family | APEX 20KC | APEX 20KC |
| Series | EP20K400 | EP20K400 |
| Device Type | Loadable PLD / FPGA | β |
| Logic Elements (Cells) | 16,640 | β |
| System Gates | 400,000 | β |
| Embedded Memory (Bits) | 212,992 | β |
| Total RAM Bits | 212,992 | β |
| Maximum User I/O | 488 | 488 (per Globalspec) / 484 (per Microchip USA) [DATA_NEEDED: confirm canonical value] |
| I/O Lines | 484 | β |
| Input Lines | 488 | β |
| Number of PLLs | 4 | β |
| Maximum Internal Clock Frequency | 375.94 MHz | β |
| Propagation Delay | 1.4 ns | 2.5 ns |
| Process Technology | 0.18 um CMOS | 0.15 Β΅m CMOS |
| Core Voltage | 1.8 V | β |
| MultiVolt I/O | 1.5 V / 1.8 V / 2.5 V / 3.3 V | β |
| Speed Grade | C7 (commercial, -7) | β |
| Operating Temperature | 0C to +85C (commercial) | 0Β°C to 85Β°C (Commercial) |
| Package Type | 672-ball FineLine BGA | β |
| Package Code | FC-FBGA-B672 | β |
| Ball Pitch | 1.000 mm | β |
| Mounting Type | Surface Mount | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: not stated in verified data] |
| Logic Cells / Macros | β | 16,640 |
| System Gates (typical) | β | 400,000 |
| System Gates (maximum) | β | 212,992 [DATA_NEEDED: confirm datasheet interpretation] |
| Bidirectional I/O | β | 484 |
| Maximum Internal Frequency | β | 301.21 MHz |
| Nominal Supply Voltage | β | 1.8 V |
| Supply Voltage Range | β | 1.71 V to 1.89 V |
| Package | β | 672-BGA FineLine (FC-FBGA / S-PBGA-B672) |
| Logic Family | β | CMOS |
| Architecture | β | MultiCoreβ’ (LUT + Embedded System Block) |
| Programming Method | β | JTAG / in-system via configuration memory |