EP20K400CF672C7ES vs EP20K400CF672C8ES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400CF672C7ES sa pamamagitan ng Altera at EP20K400CF672C8ES sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400CF672C7ES | EP20K400CF672C8ES |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Series | EP20K400 | EP20K400 |
| Device Type | Loadable PLD / FPGA | — |
| Logic Elements (Cells) | 16,640 | — |
| System Gates | 400,000 | — |
| Embedded Memory (Bits) | 212,992 | — |
| Total RAM Bits | 212,992 | — |
| Maximum User I/O | 488 | 488 (per Globalspec) / 484 (per Microchip USA) [DATA_NEEDED: confirm canonical value] |
| I/O Lines | 484 | — |
| Input Lines | 488 | — |
| Number of PLLs | 4 | — |
| Maximum Internal Clock Frequency | 375.94 MHz | — |
| Propagation Delay | 1.4 ns | 2.5 ns |
| Process Technology | 0.18 um CMOS | 0.15 µm CMOS |
| Core Voltage | 1.8 V | — |
| MultiVolt I/O | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Speed Grade | C7 (commercial, -7) | — |
| Temperature na Operasyon | 0C to +85C (commercial) | 0°C to 85°C (Commercial) |
| Package Type | 672-ball FineLine BGA | — |
| Package Code | FC-FBGA-B672 | — |
| Ball Pitch | 1.000 mm | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: not stated in verified data] |
| Logic Cells / Macros | — | 16,640 |
| System Gates (typical) | — | 400,000 |
| System Gates (maximum) | — | 212,992 [DATA_NEEDED: confirm datasheet interpretation] |
| Bidirectional I/O | — | 484 |
| Maximum Internal Frequency | — | 301.21 MHz |
| Nominal Supply Voltage | — | 1.8 V |
| Supply Voltage Range | — | 1.71 V to 1.89 V |
| Packhaging | — | 672-BGA FineLine (FC-FBGA / S-PBGA-B672) |
| Logic Family | — | CMOS |
| Architecture | — | MultiCore™ (LUT + Embedded System Block) |
| Programming Method | — | JTAG / in-system via configuration memory |