EP20K400CF672C7ES vs EP20K400CF672C8ES 对比

详细并排对比 EP20K400CF672C7ES 出自 Altera 和 EP20K400CF672C8ES 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400CF672C7ES EP20K400CF672C8ES
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $152.00 $158.40
Family APEX 20KC APEX 20KC
Series EP20K400 EP20K400
Device Type Loadable PLD / FPGA —
Logic Elements (Cells) 16,640 —
System Gates 400,000 —
Embedded Memory (Bits) 212,992 —
Total RAM Bits 212,992 —
Maximum User I/O 488 488 (per Globalspec) / 484 (per Microchip USA) [DATA_NEEDED: confirm canonical value]
I/O Lines 484 —
Input Lines 488 —
Number of PLLs 4 —
Maximum Internal Clock Frequency 375.94 MHz —
Propagation Delay 1.4 ns 2.5 ns
Process Technology 0.18 um CMOS 0.15 µm CMOS
Core Voltage 1.8 V —
MultiVolt I/O 1.5 V / 1.8 V / 2.5 V / 3.3 V —
Speed Grade C7 (commercial, -7) —
工作温度 0C to +85C (commercial) 0°C to 85°C (Commercial)
Package Type 672-ball FineLine BGA —
Package Code FC-FBGA-B672 —
Ball Pitch 1.000 mm —
安装类型 Surface Mount —
RoHS 状态 [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: not stated in verified data]
Logic Cells / Macros — 16,640
System Gates (typical) — 400,000
System Gates (maximum) — 212,992 [DATA_NEEDED: confirm datasheet interpretation]
Bidirectional I/O — 484
Maximum Internal Frequency — 301.21 MHz
Nominal Supply Voltage — 1.8 V
Supply Voltage Range — 1.71 V to 1.89 V
封装 — 672-BGA FineLine (FC-FBGA / S-PBGA-B672)
Logic Family — CMOS
Architecture — MultiCore™ (LUT + Embedded System Block)
Programming Method — JTAG / in-system via configuration memory

数据手册与资源

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