EP20K400FI672-3N vs EP20K400FI672-3X Comparison

Detailed side-by-side comparison of EP20K400FI672-3N by Altera and EP20K400FI672-3X by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EP20K400FI672-3N EP20K400FI672-3N - 833 MHz FPGA, 502 I/O, 672-PBGA

EP20K400FI672-3N - 833 MHz FPGA, 502 I/O, 672-PBGA

EP20K400FI672-3N Unknown
Altera
EP20K400FI672-3X EP20K400FI672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera/Intel

EP20K400FI672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera/Intel

EP20K400FI672-3X ⚠ Last Time Buy

Specification Comparison

Parameter EP20K400FI672-3N EP20K400FI672-3X
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Unknown Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $142.00
Device Type CMOS loadable programmable logic device β€”
Product Family APEX 20K β€”
Series EP20K400 β€”
Propagation Delay 3.6 ns β€”
Maximum Clock Frequency 833 MHz β€”
User I/O Count 502 β€”
Nominal Supply Voltage 2.5 V β€”
Supply Voltage Range 2.375 V to 2.625 V β€”
Process Technology CMOS β€”
Package S-PBGA-B672 672-ball Fine-Pitch BGA (S-PBGA-B672)
Terminal Count 672 terminals β€”
Terminal Pitch 1.000 mm 1.000 mm
Mounting Type Surface mount Surface Mount
Logic Capacity [DATA_NEEDED: logic capacity] β€”
Operating Temperature [DATA_NEEDED: operating temperature range] β€”
Configuration Method [DATA_NEEDED: configuration method] β€”
I/O Standard Support [DATA_NEEDED: supported I/O standards] β€”
RoHS Status unknown Compliant (per Intel/Altera product page)
REACH Status unknown β€”
AEC-Q100 Qualification unknown β€”
Family β€” APEX 20K
Device Series β€” EP20K400
Maximum System Gates β€” 400,000
Maximum Logic Elements β€” [DATA_NEEDED: exact LE count for EP20K400]
Maximum User I/O β€” 502
Nominal Core Voltage (VCCINT) β€” 2.5 V
VCCINT Range β€” 2.375 V to 2.625 V
Typical Propagation Delay β€” 3.6 ns
Maximum Internal Clock Frequency β€” 833 MHz
Technology β€” CMOS SRAM configuration cell
Speed Grade β€” -3 (high-performance tier)
Temperature Grade (X suffix) β€” Industrial / extended
Moisture Sensitivity Level (MSL) β€” 3
Peak Reflow Temperature β€” 220 C

Datasheets & Resources

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