EP20K400FI672-3N vs EP20K400FI672-3X Comparaison
Comparaison détaillée côte à côte de EP20K400FI672-3N par Altera et EP20K400FI672-3X par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP20K400FI672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera/Intel
EP20K400FI672-3X ⚠ Dernier achatComparaison des spécifications
| Paramètre | EP20K400FI672-3N | EP20K400FI672-3X |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Unknown | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $142,00 |
| Device Type | CMOS loadable programmable logic device | — |
| Product Family | APEX 20K | — |
| Series | EP20K400 | — |
| Propagation Delay | 3.6 ns | — |
| Fréquence d'horloge maximale | 833 MHz | — |
| User I/O Count | 502 | — |
| Nominal Supply Voltage | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | — |
| Process Technology | CMOS | — |
| Boîtier | S-PBGA-B672 | 672-ball Fine-Pitch BGA (S-PBGA-B672) |
| Terminal Count | 672 terminals | — |
| Terminal Pitch | 1.000 mm | 1.000 mm |
| Type de montage | Surface mount | Surface Mount |
| Logic Capacity | [DATA_NEEDED: logic capacity] | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | — |
| Configuration Method | [DATA_NEEDED: configuration method] | — |
| I/O Standard Support | [DATA_NEEDED: supported I/O standards] | — |
| Statut RoHS | unknown | Compliant (per Intel/Altera product page) |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Family | — | APEX 20K |
| Device Series | — | EP20K400 |
| Maximum System Gates | — | 400,000 |
| Maximum Logic Elements | — | [DATA_NEEDED: exact LE count for EP20K400] |
| Maximum User I/O | — | 502 |
| Nominal Core Voltage (VCCINT) | — | 2.5 V |
| VCCINT Range | — | 2.375 V to 2.625 V |
| Typical Propagation Delay | — | 3.6 ns |
| Maximum Internal Clock Frequency | — | 833 MHz |
| Technology | — | CMOS SRAM configuration cell |
| Speed Grade | — | -3 (high-performance tier) |
| Temperature Grade (X suffix) | — | Industrial / extended |
| Niveau de sensibilité à l'humidité (MSL) | — | 3 |
| Peak Reflow Temperature | — | 220 C |