EP20K400FI672-3N vs EP20K400FI672-3X 比較
詳細並排比較 EP20K400FI672-3N 由 Altera 與 EP20K400FI672-3X 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP20K400FI672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera/Intel
EP20K400FI672-3X ⚠ 最後購買機會規格比較
| 參數 | EP20K400FI672-3N | EP20K400FI672-3X |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Unknown | 最後購買 |
| Device Type | CMOS loadable programmable logic device | — |
| Product Family | APEX 20K | — |
| Series | EP20K400 | — |
| Propagation Delay | 3.6 ns | — |
| 最大時脈頻率 | 833 MHz | — |
| User I/O Count | 502 | — |
| Nominal Supply Voltage | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | — |
| Process Technology | CMOS | — |
| 封裝 | S-PBGA-B672 | 672-ball Fine-Pitch BGA (S-PBGA-B672) |
| Terminal Count | 672 terminals | — |
| Terminal Pitch | 1.000 mm | 1.000 mm |
| 安裝類型 | Surface mount | Surface Mount |
| Logic Capacity | [DATA_NEEDED: logic capacity] | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | — |
| Configuration Method | [DATA_NEEDED: configuration method] | — |
| I/O Standard Support | [DATA_NEEDED: supported I/O standards] | — |
| RoHS 狀態 | unknown | Compliant (per Intel/Altera product page) |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Family | — | APEX 20K |
| Device Series | — | EP20K400 |
| Maximum System Gates | — | 400,000 |
| Maximum Logic Elements | — | [DATA_NEEDED: exact LE count for EP20K400] |
| Maximum User I/O | — | 502 |
| Nominal Core Voltage (VCCINT) | — | 2.5 V |
| VCCINT Range | — | 2.375 V to 2.625 V |
| Typical Propagation Delay | — | 3.6 ns |
| Maximum Internal Clock Frequency | — | 833 MHz |
| Technology | — | CMOS SRAM configuration cell |
| Speed Grade | — | -3 (high-performance tier) |
| Temperature Grade (X suffix) | — | Industrial / extended |
| 濕度敏感等級 (MSL) | — | 3 |
| Peak Reflow Temperature | — | 220 C |