EP20K400GC655-1X vs EP20K400GC655-2N Comparison

Detailed side-by-side comparison of EP20K400GC655-1X by Altera and EP20K400GC655-2N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EP20K400GC655-1X EP20K400GC655-1X - 400K-Gate APEX 20K FPGA | Altera

EP20K400GC655-1X - 400K-Gate APEX 20K FPGA | Altera

EP20K400GC655-1X Obsolete

Specification Comparison

Parameter EP20K400GC655-1X EP20K400GC655-2N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $193.04 $127.50
Product Family Altera APEX 20K β€”
Device Type Field Programmable Gate Array (FPGA) β€”
Technology CMOS β€”
Gate Count 400K gates β€”
Logic Elements 16640 cells β€”
Maximum System Frequency 250 MHz β€”
Propagation Delay 2.5 ns β€”
Core Supply Voltage 2.5 V β€”
I/O Supply Voltage 2.5 V / 3.3 V β€”
Number of User I/O 496 β€”
Number of Dedicated Inputs 6 β€”
Number of Terminals 655 β€”
Package Type CPGA-655 (Ceramic Pin Grid Array) β€”
Package Body Material Ceramic β€”
Process Technology 0.22 um 0.22 Β΅m CMOS
Operating Temperature Range [DATA_NEEDED: operating temperature range] β€”
Embedded RAM Bits [DATA_NEEDED: embedded RAM bits] β€”
RoHS Status unknown [DATA_NEEDED: RoHS status]
Family β€” APEX 20KC
Number of Logic Elements β€” 16640
Number of Logic Cells β€” 16640
Total System Gates β€” 400000
Total RAM Bits β€” 212992
Number of I/O β€” [DATA_NEEDED: I/O count]
Number of LABs/CLBs β€” [DATA_NEEDED: LAB count]
Core Voltage (VCCINT) β€” 1.71 V to 1.89 V
I/O Voltage (VCCIO) β€” 2.5 V (LVDS-capable)
Maximum Operating Frequency β€” 200 MHz
Propagation Delay (Tpd) β€” 3.1 ns
Package / Case β€” 655-BCPGA (Ceramic Pin Grid Array)
Supplier Device Package β€” 655-CPGA, 62.48 x 62.48 mm
Operating Temperature β€” Industrial (per Altera part-number -N suffix)
Mounting Type β€” Through-Hole (CPGA, socket-compatible)
LVDS Support β€” Yes
Architecture β€” MultiCore (LUT + product-term + embedded memory)
Configuration Method β€” JTAG / Passive Serial
MSL Level β€” [DATA_NEEDED: MSL level]

Datasheets & Resources

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