EP20K400GC655-1X vs EP20K400GC655-2N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GC655-1X sa pamamagitan ng Altera at EP20K400GC655-2N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EP20K400GC655-1X EP20K400GC655-1X - 400K-Gate APEX 20K FPGA | Altera

EP20K400GC655-1X - 400K-Gate APEX 20K FPGA | Altera

EP20K400GC655-1X Obsolete

Pagsanggunian na paghahambing

Parametro EP20K400GC655-1X EP20K400GC655-2N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Family Altera APEX 20K —
Device Type Field Programmable Gate Array (FPGA) —
Technology CMOS —
Gate Count 400K gates —
Logic Elements 16640 cells —
Maximum System Frequency 250 MHz —
Propagation Delay 2.5 ns —
Core Supply Voltage 2.5 V —
I/O Supply Voltage 2.5 V / 3.3 V —
Number of User I/O 496 —
Number of Dedicated Inputs 6 —
Number of Terminals 655 —
Package Type CPGA-655 (Ceramic Pin Grid Array) —
Package Body Material Ceramic —
Process Technology 0.22 um 0.22 µm CMOS
Hanay ng Temperature na Operasyon [DATA_NEEDED: operating temperature range] —
Embedded RAM Bits [DATA_NEEDED: embedded RAM bits] —
Tindminan RoHS unknown [DATA_NEEDED: RoHS status]
Family — APEX 20KC
Number of Logic Elements — 16640
Number of Logic Cells — 16640
Total System Gates — 400000
Total RAM Bits — 212992
Number of I/O — [DATA_NEEDED: I/O count]
Number of LABs/CLBs — [DATA_NEEDED: LAB count]
Core Voltage (VCCINT) — 1.71 V to 1.89 V
I/O Voltage (VCCIO) — 2.5 V (LVDS-capable)
Maximum Operating Frequency — 200 MHz
Propagation Delay (Tpd) — 3.1 ns
Packhaging / Kaso — 655-BCPGA (Ceramic Pin Grid Array)
Supplier Device Package — 655-CPGA, 62.48 x 62.48 mm
Temperature na Operasyon — Industrial (per Altera part-number -N suffix)
Uri ng Pagpapasok — Through-Hole (CPGA, socket-compatible)
LVDS Support — Yes
Architecture — MultiCore (LUT + product-term + embedded memory)
Configuration Method — JTAG / Passive Serial
Level ng MSL — [DATA_NEEDED: MSL level]

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