EP20K400GC655-2X vs EP20K400GC655-1 Comparison
Detailed side-by-side comparison of EP20K400GC655-2X by Altera and EP20K400GC655-1 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoleteSpecification Comparison
| Parameter | EP20K400GC655-2X | EP20K400GC655-1 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $175.00 | $135.00 |
| Family | APEX 20K | APEX 20K |
| Series | APEX-20KCยฎ | EP20K400 |
| Logic Elements / Cells | 16640 | โ |
| System Gates | 400000 | โ |
| Total RAM Bits | 212992 | 212,992 |
| Number of I/O | 496 | โ |
| Number of Dedicated Inputs | 6 | โ |
| Number of LABs/CLBs | [DATA_NEEDED: number of Logic Array Blocks] | โ |
| Number of EABs | [DATA_NEEDED: number of Embedded Array Blocks] | โ |
| Maximum Operating Frequency | 200 MHz | โ |
| Process Technology | 0.22 ยตm CMOS | 0.22 ยตm CMOS |
| Core Supply Voltage | 2.5 V | 2.5 V |
| I/O Supply Voltage (MultiVolt) | 2.5 V / 3.3 V / 5 V | โ |
| Package Type | 655-BCPGA (SPGA655) | โ |
| Package Body Material | CERAMIC, metal-sealed cofired grid array | โ |
| Package Dimensions | 47 x 47 mm | โ |
| Peak Reflow Temperature | 220 ยฐC | โ |
| Mounting Type | Through-hole (CPGA) | Through-Hole |
| Programmability | In-system, JTAG (IEEE 1149.1) | โ |
| Operating Temperature | [DATA_NEEDED: temperature grade] | 0 ยฐC to +85 ยฐC (commercial) |
| RoHS Status | unknown | Non-compliant (contains lead in ceramic package) |
| Logic Elements | โ | 16,640 |
| Maximum Gates | โ | 1,052,000 |
| Typical Gates | โ | 400,000 |
| Embedded System Blocks (ESBs) | โ | 4 |
| Maximum User I/O | โ | 502 |
| Dedicated Inputs | โ | 6 |
| I/O Supply Voltage | โ | 3.3 V |
| Maximum Internal Frequency | โ | 250 MHz |
| Propagation Delay | โ | 2.5 ns |
| Package | โ | 655-pin CPGA (Ceramic Pin Grid Array) |
| Pin Count | โ | 655 |
| Configuration Modes | โ | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | โ | IEEE 1149.1 (JTAG) |