EP20K400GC655-2X vs EP20K400GC655-1 Vergleich
Detaillierter Direktvergleich von EP20K400GC655-2X von Altera und EP20K400GC655-1 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoleteSpezifikationsvergleich
| Parameter | EP20K400GC655-2X | EP20K400GC655-1 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $175,00 | $135,00 |
| Family | APEX 20K | APEX 20K |
| Series | APEX-20KC® | EP20K400 |
| Logic Elements / Cells | 16640 | — |
| System Gates | 400000 | — |
| Total RAM Bits | 212992 | 212,992 |
| Number of I/O | 496 | — |
| Number of Dedicated Inputs | 6 | — |
| Number of LABs/CLBs | [DATA_NEEDED: number of Logic Array Blocks] | — |
| Number of EABs | [DATA_NEEDED: number of Embedded Array Blocks] | — |
| Maximum Operating Frequency | 200 MHz | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V | 2.5 V |
| I/O Supply Voltage (MultiVolt) | 2.5 V / 3.3 V / 5 V | — |
| Package Type | 655-BCPGA (SPGA655) | — |
| Package Body Material | CERAMIC, metal-sealed cofired grid array | — |
| Package Dimensions | 47 x 47 mm | — |
| Peak Reflow Temperature | 220 °C | — |
| Montageart | Through-hole (CPGA) | Through-Hole |
| Programmability | In-system, JTAG (IEEE 1149.1) | — |
| Betriebstemperatur | [DATA_NEEDED: temperature grade] | 0 °C to +85 °C (commercial) |
| RoHS-Status | unknown | Non-compliant (contains lead in ceramic package) |
| Logic Elements | — | 16,640 |
| Maximum Gates | — | 1,052,000 |
| Typical Gates | — | 400,000 |
| Embedded System Blocks (ESBs) | — | 4 |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 6 |
| I/O Supply Voltage | — | 3.3 V |
| Maximum Internal Frequency | — | 250 MHz |
| Propagation Delay | — | 2.5 ns |
| Gehäuse | — | 655-pin CPGA (Ceramic Pin Grid Array) |
| Pin-Anzahl | — | 655 |
| Configuration Modes | — | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |