EP20K400GC655-2X vs EP20K400GC655-1 对比

详细并排对比 EP20K400GC655-2X 出自 Altera 和 EP20K400GC655-1 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K400GC655-2X EP20K400GC655-1
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $175.00 $135.00
Family APEX 20K APEX 20K
Series APEX-20KC® EP20K400
Logic Elements / Cells 16640 —
System Gates 400000 —
Total RAM Bits 212992 212,992
Number of I/O 496 —
Number of Dedicated Inputs 6 —
Number of LABs/CLBs [DATA_NEEDED: number of Logic Array Blocks] —
Number of EABs [DATA_NEEDED: number of Embedded Array Blocks] —
Maximum Operating Frequency 200 MHz —
Process Technology 0.22 µm CMOS 0.22 µm CMOS
Core Supply Voltage 2.5 V 2.5 V
I/O Supply Voltage (MultiVolt) 2.5 V / 3.3 V / 5 V —
Package Type 655-BCPGA (SPGA655) —
Package Body Material CERAMIC, metal-sealed cofired grid array —
Package Dimensions 47 x 47 mm —
Peak Reflow Temperature 220 °C —
安装类型 Through-hole (CPGA) Through-Hole
Programmability In-system, JTAG (IEEE 1149.1) —
工作温度 [DATA_NEEDED: temperature grade] 0 °C to +85 °C (commercial)
RoHS 状态 unknown Non-compliant (contains lead in ceramic package)
Logic Elements — 16,640
Maximum Gates — 1,052,000
Typical Gates — 400,000
Embedded System Blocks (ESBs) — 4
Maximum User I/O — 502
Dedicated Inputs — 6
I/O Supply Voltage — 3.3 V
Maximum Internal Frequency — 250 MHz
Propagation Delay — 2.5 ns
封装 — 655-pin CPGA (Ceramic Pin Grid Array)
引脚数量 — 655
Configuration Modes — Passive Serial, Passive Parallel Async, Passive Parallel Sync
Boundary Scan — IEEE 1149.1 (JTAG)

数据手册与资源

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