EP20K400GC655-3 vs EP20K400GI655-1 Comparison
Detailed side-by-side comparison of EP20K400GC655-3 by Intel and EP20K400GI655-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400GC655-3 | EP20K400GI655-1 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $310.00 | $195.00 |
| Series | APEX-20KC | β |
| Family | APEX 20K | APEX 20K |
| Manufacturer | Intel (formerly Altera) | β |
| Logic Elements | 16640 | 16640 |
| Total RAM Bits | 212992 | β |
| Number of Gates | 400000 | β |
| Supply Voltage - Core | 1.71 V to 1.89 V (1.8 V nominal) | β |
| I/O Voltage Tolerance | MultiVolt I/O: 1.8 V / 2.5 V / 3.3 V / 5 V | β |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (Industrial) |
| Maximum Frequency | 167 MHz (per FPGAkey) | β |
| Process Technology | 0.22 um CMOS | β |
| Package / Case | 655-BCPGA | β |
| Supplier Device Package | 655-CPGA (62.48 x 62.48 mm) | β |
| Speed Grade | -3 (slowest grade in family) | β |
| Propagation Delay (tPD) | 3.6 ns (per Microchip USA listing) | β |
| JTAG Support | IEEE 1149.1 Boundary-Scan | β |
| Configuration Modes | Passive Serial, Passive Parallel Sync/Async, Active Serial | β |
| RoHS Status | [DATA_NEEDED: rohs status] | Compliant |
| Device Series | β | EP20K400 |
| Technology | β | CMOS, SRAM-based |
| Typical Gates | β | 400000 |
| Maximum User I/O | β | 502 |
| Dedicated Inputs | β | 4 |
| Total Terminals | β | 655 |
| Propagation Delay | β | 2.5 ns |
| Package Type | β | Ceramic Pin Grid Array (CPGA-655) |
| JESD-30 Package Code | β | S-CPGA-P655 |
| Moisture Sensitivity Level | β | MSL 1 |
| Peak Reflow Temperature | β | 220 C |
| Programmability | β | In-system, JTAG boundary-scan (IEEE 1149.1) |
| Process Node | β | 0.18 micrometer CMOS |