EP20K400GC655-3 vs EP20K400GI655-1 Comparaison
Comparaison détaillée côte à côte de EP20K400GC655-3 par Intel et EP20K400GI655-1 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K400GC655-3 | EP20K400GI655-1 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $310,00 | $195,00 |
| Series | APEX-20KC | — |
| Family | APEX 20K | APEX 20K |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements | 16640 | 16640 |
| Total RAM Bits | 212992 | — |
| Number of Gates | 400000 | — |
| Supply Voltage - Core | 1.71 V to 1.89 V (1.8 V nominal) | — |
| I/O Voltage Tolerance | MultiVolt I/O: 1.8 V / 2.5 V / 3.3 V / 5 V | — |
| Température de fonctionnement | -40C to +85C (industrial) | -40C to +85C (Industrial) |
| Maximum Frequency | 167 MHz (per FPGAkey) | — |
| Process Technology | 0.22 um CMOS | — |
| Boîtier / Format | 655-BCPGA | — |
| Supplier Device Package | 655-CPGA (62.48 x 62.48 mm) | — |
| Speed Grade | -3 (slowest grade in family) | — |
| Propagation Delay (tPD) | 3.6 ns (per Microchip USA listing) | — |
| JTAG Support | IEEE 1149.1 Boundary-Scan | — |
| Configuration Modes | Passive Serial, Passive Parallel Sync/Async, Active Serial | — |
| Statut RoHS | [DATA_NEEDED: rohs status] | Compliant |
| Device Series | — | EP20K400 |
| Technology | — | CMOS, SRAM-based |
| Typical Gates | — | 400000 |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 4 |
| Total Terminals | — | 655 |
| Propagation Delay | — | 2.5 ns |
| Package Type | — | Ceramic Pin Grid Array (CPGA-655) |
| JESD-30 Package Code | — | S-CPGA-P655 |
| Moisture Sensitivity Level | — | MSL 1 |
| Peak Reflow Temperature | — | 220 C |
| Programmability | — | In-system, JTAG boundary-scan (IEEE 1149.1) |
| Process Node | — | 0.18 micrometer CMOS |