EP20K400GC655-3 vs EP20K400GI655-1 对比
详细并排对比 EP20K400GC655-3 出自 Intel 和 EP20K400GI655-1 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP20K400GC655-3 | EP20K400GI655-1 |
|---|---|---|
| 品牌 | Intel | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 最后采购期 | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $310.00 | $195.00 |
| Series | APEX-20KC | — |
| Family | APEX 20K | APEX 20K |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements | 16640 | 16640 |
| Total RAM Bits | 212992 | — |
| Number of Gates | 400000 | — |
| Supply Voltage - Core | 1.71 V to 1.89 V (1.8 V nominal) | — |
| I/O Voltage Tolerance | MultiVolt I/O: 1.8 V / 2.5 V / 3.3 V / 5 V | — |
| 工作温度 | -40C to +85C (industrial) | -40C to +85C (Industrial) |
| Maximum Frequency | 167 MHz (per FPGAkey) | — |
| Process Technology | 0.22 um CMOS | — |
| 封装 / 外壳 | 655-BCPGA | — |
| Supplier Device Package | 655-CPGA (62.48 x 62.48 mm) | — |
| Speed Grade | -3 (slowest grade in family) | — |
| Propagation Delay (tPD) | 3.6 ns (per Microchip USA listing) | — |
| JTAG Support | IEEE 1149.1 Boundary-Scan | — |
| Configuration Modes | Passive Serial, Passive Parallel Sync/Async, Active Serial | — |
| RoHS 状态 | [DATA_NEEDED: rohs status] | Compliant |
| Device Series | — | EP20K400 |
| Technology | — | CMOS, SRAM-based |
| Typical Gates | — | 400000 |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 4 |
| Total Terminals | — | 655 |
| Propagation Delay | — | 2.5 ns |
| Package Type | — | Ceramic Pin Grid Array (CPGA-655) |
| JESD-30 Package Code | — | S-CPGA-P655 |
| Moisture Sensitivity Level | — | MSL 1 |
| Peak Reflow Temperature | — | 220 C |
| Programmability | — | In-system, JTAG boundary-scan (IEEE 1149.1) |
| Process Node | — | 0.18 micrometer CMOS |