EP20K400GI655-2 vs EP20K400GI655-3 Comparison

Detailed side-by-side comparison of EP20K400GI655-2 by Altera and EP20K400GI655-3 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K400GI655-2 EP20K400GI655-3
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $175.00 $55.00
Manufacturer Altera Corporation β€”
Series APEX 20K (EP20K400) β€”
Device Type Field Programmable Gate Array (FPGA) β€”
Typical Gate Count 400,000 gates β€”
Logic Elements (LE) 16,640 β€”
Maximum User I/O 496 502
Dedicated Inputs 6 4
Number of Terminals 655 655
Package SPGA-655 (47 mm x 47 mm) 655-Pin PGA (Plastic/CPGA, square)
Nominal Supply Voltage 2.5 V β€”
Supply Voltage Range 2.375 V to 2.625 V β€”
Propagation Delay 3.1 ns (typical) β€”
Technology CMOS SRAM β€”
Operating Temperature -40C to +85C (industrial) 0Β°C to 70Β°C (Industrial I grade)
Mounting Type Through-Hole / Socket Through-Hole (Socket)
Moisture Sensitivity Level 1 (per Altera family) β€”
Configuration Method JTAG, Passive Serial, Passive Parallel β€”
I/O Standards Supported LVTTL, LVCMOS, PCI, GTL+ β€”
Embedded Memory Embedded System Blocks (ESBs) Dual-port RAM via Embedded System Blocks (ESBs)
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Lifecycle Status Obsolete (legacy Altera APEX 20K family) β€”
Family β€” APEX 20KE
Logic Elements / Cells β€” 16,640
System Gates β€” 400,000 (maximum)
JESD-30 Code β€” S-CPGA-P655
Package Shape β€” Square
Form of Terminal β€” PIN/PEG (through-hole)
Process Technology β€” CMOS, 2.5V core
Core Supply Voltage β€” 2.5 V
I/O Supply Voltage β€” 2.5 V or 3.3 V (MultiVolt I/O)
Speed Grade β€” -3 (slowest of the EP20K400 family)
Configuration Modes β€” Passive Serial, Passive Parallel Asynchronous, JTAG
JTAG / Boundary Scan β€” IEEE 1149.1 compliant

Datasheets & Resources

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