EP20K400GI655-2 vs EP20K400GI655-3 比較
詳細並排比較 EP20K400GI655-2 由 Altera 與 EP20K400GI655-3 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400GI655-2 | EP20K400GI655-3 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Manufacturer | Altera Corporation | — |
| Series | APEX 20K (EP20K400) | — |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Typical Gate Count | 400,000 gates | — |
| Logic Elements (LE) | 16,640 | — |
| Maximum User I/O | 496 | 502 |
| Dedicated Inputs | 6 | 4 |
| Number of Terminals | 655 | 655 |
| 封裝 | SPGA-655 (47 mm x 47 mm) | 655-Pin PGA (Plastic/CPGA, square) |
| Nominal Supply Voltage | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | — |
| Propagation Delay | 3.1 ns (typical) | — |
| Technology | CMOS SRAM | — |
| 工作溫度 | -40C to +85C (industrial) | 0°C to 70°C (Industrial I grade) |
| 安裝類型 | Through-Hole / Socket | Through-Hole (Socket) |
| Moisture Sensitivity Level | 1 (per Altera family) | — |
| Configuration Method | JTAG, Passive Serial, Passive Parallel | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+ | — |
| Embedded Memory | Embedded System Blocks (ESBs) | Dual-port RAM via Embedded System Blocks (ESBs) |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| 生命週期狀態 | Obsolete (legacy Altera APEX 20K family) | — |
| Family | — | APEX 20KE |
| Logic Elements / Cells | — | 16,640 |
| System Gates | — | 400,000 (maximum) |
| JESD-30 Code | — | S-CPGA-P655 |
| Package Shape | — | Square |
| Form of Terminal | — | PIN/PEG (through-hole) |
| Process Technology | — | CMOS, 2.5V core |
| Core Supply Voltage | — | 2.5 V |
| I/O Supply Voltage | — | 2.5 V or 3.3 V (MultiVolt I/O) |
| Speed Grade | — | -3 (slowest of the EP20K400 family) |
| Configuration Modes | — | Passive Serial, Passive Parallel Asynchronous, JTAG |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |