EP20K400GI655-2 vs EP20K400GI655-3 Comparaison
Comparaison détaillée côte à côte de EP20K400GI655-2 par Altera et EP20K400GI655-3 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K400GI655-2 | EP20K400GI655-3 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $175,00 | $55,00 |
| Manufacturer | Altera Corporation | — |
| Series | APEX 20K (EP20K400) | — |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Typical Gate Count | 400,000 gates | — |
| Logic Elements (LE) | 16,640 | — |
| Maximum User I/O | 496 | 502 |
| Dedicated Inputs | 6 | 4 |
| Number of Terminals | 655 | 655 |
| Boîtier | SPGA-655 (47 mm x 47 mm) | 655-Pin PGA (Plastic/CPGA, square) |
| Nominal Supply Voltage | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | — |
| Propagation Delay | 3.1 ns (typical) | — |
| Technology | CMOS SRAM | — |
| Température de fonctionnement | -40C to +85C (industrial) | 0°C to 70°C (Industrial I grade) |
| Type de montage | Through-Hole / Socket | Through-Hole (Socket) |
| Moisture Sensitivity Level | 1 (per Altera family) | — |
| Configuration Method | JTAG, Passive Serial, Passive Parallel | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+ | — |
| Embedded Memory | Embedded System Blocks (ESBs) | Dual-port RAM via Embedded System Blocks (ESBs) |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Statut du cycle de vie | Obsolete (legacy Altera APEX 20K family) | — |
| Family | — | APEX 20KE |
| Logic Elements / Cells | — | 16,640 |
| System Gates | — | 400,000 (maximum) |
| JESD-30 Code | — | S-CPGA-P655 |
| Package Shape | — | Square |
| Form of Terminal | — | PIN/PEG (through-hole) |
| Process Technology | — | CMOS, 2.5V core |
| Core Supply Voltage | — | 2.5 V |
| I/O Supply Voltage | — | 2.5 V or 3.3 V (MultiVolt I/O) |
| Speed Grade | — | -3 (slowest of the EP20K400 family) |
| Configuration Modes | — | Passive Serial, Passive Parallel Asynchronous, JTAG |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |