EP20K400GI655-2X vs EP20K400GI655-1 Comparison
Detailed side-by-side comparison of EP20K400GI655-2X by Intel and EP20K400GI655-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400GI655-2X | EP20K400GI655-1 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $195.00 | $195.00 |
| Series | APEX-20K | β |
| Family | APEX-20K (loadable PLD / FPGA) | APEX 20K |
| Logic Elements (LEs) | 16,640 | β |
| System Gates | 400,000 | β |
| Maximum User I/O | 502 | 502 |
| Total I/O Lines | 496 (bidirectional) + 4 (dedicated inputs) | β |
| Embedded Memory (bits) | 212,992 | β |
| Nominal Core Supply Voltage | 2.5 V | β |
| Supply Voltage Range | 2.375 V to 2.625 V | β |
| I/O Supply Voltages | 2.5 V / 3.3 V | β |
| Process Technology | CMOS | β |
| Propagation Delay (typical, -2 grade) | 3.1 ns | β |
| Package | 655-ball FineLine BGA (SPGA655, 47x47 mm) | β |
| Package Code | SPGA655, 47x47 | β |
| Surface Mount | Yes (BGA) | β |
| Moisture Sensitivity Level (MSL) | 1 | β |
| Operating Temperature (industrial -X grade) | -40C to +85C (industrial) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | Compliant |
| Qualification | Not Qualified (per distributor listing) | β |
| JTAG Support | IEEE 1149.1 boundary-scan / programming | β |
| Device Series | β | EP20K400 |
| Technology | β | CMOS, SRAM-based |
| Logic Elements | β | 16640 |
| Typical Gates | β | 400000 |
| Dedicated Inputs | β | 4 |
| Total Terminals | β | 655 |
| Propagation Delay | β | 2.5 ns |
| Package Type | β | Ceramic Pin Grid Array (CPGA-655) |
| JESD-30 Package Code | β | S-CPGA-P655 |
| Operating Temperature | β | -40C to +85C (Industrial) |
| Moisture Sensitivity Level | β | MSL 1 |
| Peak Reflow Temperature | β | 220 C |
| Programmability | β | In-system, JTAG boundary-scan (IEEE 1149.1) |
| Process Node | β | 0.18 micrometer CMOS |