EP20K400GI655-2X vs EP20K400GI655-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GI655-2X sa pamamagitan ng Intel at EP20K400GI655-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400GI655-2X | EP20K400GI655-1 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | APEX-20K | — |
| Family | APEX-20K (loadable PLD / FPGA) | APEX 20K |
| Logic Elements (LEs) | 16,640 | — |
| System Gates | 400,000 | — |
| Maximum User I/O | 502 | 502 |
| Total I/O Lines | 496 (bidirectional) + 4 (dedicated inputs) | — |
| Embedded Memory (bits) | 212,992 | — |
| Nominal Core Supply Voltage | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | — |
| I/O Supply Voltages | 2.5 V / 3.3 V | — |
| Process Technology | CMOS | — |
| Propagation Delay (typical, -2 grade) | 3.1 ns | — |
| Packhaging | 655-ball FineLine BGA (SPGA655, 47x47 mm) | — |
| Package Code | SPGA655, 47x47 | — |
| Surface Mount | Yes (BGA) | — |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | 1 | — |
| Operating Temperature (industrial -X grade) | -40C to +85C (industrial) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | Compliant |
| Qualification | Not Qualified (per distributor listing) | — |
| JTAG Support | IEEE 1149.1 boundary-scan / programming | — |
| Device Series | — | EP20K400 |
| Technology | — | CMOS, SRAM-based |
| Logic Elements | — | 16640 |
| Typical Gates | — | 400000 |
| Dedicated Inputs | — | 4 |
| Total Terminals | — | 655 |
| Propagation Delay | — | 2.5 ns |
| Package Type | — | Ceramic Pin Grid Array (CPGA-655) |
| JESD-30 Package Code | — | S-CPGA-P655 |
| Temperature na Operasyon | — | -40C to +85C (Industrial) |
| Moisture Sensitivity Level | — | MSL 1 |
| Peak Reflow Temperature | — | 220 C |
| Programmability | — | In-system, JTAG boundary-scan (IEEE 1149.1) |
| Process Node | — | 0.18 micrometer CMOS |