EP20K400GI655-2X vs EP20K400GI655-1 Comparación
Comparación detallada lado a lado de EP20K400GI655-2X por Intel y EP20K400GI655-1 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K400GI655-2X | EP20K400GI655-1 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $195,00 | $195,00 |
| Series | APEX-20K | — |
| Family | APEX-20K (loadable PLD / FPGA) | APEX 20K |
| Logic Elements (LEs) | 16,640 | — |
| System Gates | 400,000 | — |
| Maximum User I/O | 502 | 502 |
| Total I/O Lines | 496 (bidirectional) + 4 (dedicated inputs) | — |
| Embedded Memory (bits) | 212,992 | — |
| Nominal Core Supply Voltage | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | — |
| I/O Supply Voltages | 2.5 V / 3.3 V | — |
| Process Technology | CMOS | — |
| Propagation Delay (typical, -2 grade) | 3.1 ns | — |
| Encapsulado | 655-ball FineLine BGA (SPGA655, 47x47 mm) | — |
| Package Code | SPGA655, 47x47 | — |
| Surface Mount | Yes (BGA) | — |
| Nivel de sensibilidad a la humedad (MSL) | 1 | — |
| Operating Temperature (industrial -X grade) | -40C to +85C (industrial) | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | Compliant |
| Qualification | Not Qualified (per distributor listing) | — |
| JTAG Support | IEEE 1149.1 boundary-scan / programming | — |
| Device Series | — | EP20K400 |
| Technology | — | CMOS, SRAM-based |
| Logic Elements | — | 16640 |
| Typical Gates | — | 400000 |
| Dedicated Inputs | — | 4 |
| Total Terminals | — | 655 |
| Propagation Delay | — | 2.5 ns |
| Package Type | — | Ceramic Pin Grid Array (CPGA-655) |
| JESD-30 Package Code | — | S-CPGA-P655 |
| Temperatura de funcionamiento | — | -40C to +85C (Industrial) |
| Moisture Sensitivity Level | — | MSL 1 |
| Peak Reflow Temperature | — | 220 C |
| Programmability | — | In-system, JTAG boundary-scan (IEEE 1149.1) |
| Process Node | — | 0.18 micrometer CMOS |