EP20K400GI655-2X vs EP20K400GI655-1X Comparison

Detailed side-by-side comparison of EP20K400GI655-2X by Intel and EP20K400GI655-1X by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K400GI655-2X EP20K400GI655-1X
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $195.00 $160.00
Series APEX-20K β€”
Family APEX-20K (loadable PLD / FPGA) APEX 20K
Logic Elements (LEs) 16,640 β€”
System Gates 400,000 β€”
Maximum User I/O 502 β€”
Total I/O Lines 496 (bidirectional) + 4 (dedicated inputs) β€”
Embedded Memory (bits) 212,992 β€”
Nominal Core Supply Voltage 2.5 V β€”
Supply Voltage Range 2.375 V to 2.625 V β€”
I/O Supply Voltages 2.5 V / 3.3 V β€”
Process Technology CMOS CMOS, SRAM-based configuration
Propagation Delay (typical, -2 grade) 3.1 ns β€”
Package 655-ball FineLine BGA (SPGA655, 47x47 mm) β€”
Package Code SPGA655, 47x47 β€”
Surface Mount Yes (BGA) β€”
Moisture Sensitivity Level (MSL) 1 1
Operating Temperature (industrial -X grade) -40C to +85C (industrial) β€”
RoHS Status [DATA_NEEDED: RoHS compliance] Compliant
Qualification Not Qualified (per distributor listing) β€”
JTAG Support IEEE 1149.1 boundary-scan / programming β€”
Device β€” EP20K400
Logic Elements β€” 16640
Number of Terminals β€” 655
User I/O Lines β€” 502
Dedicated Inputs β€” 4
Package Type β€” Ceramic Pin Grid Array (CPGA)
Package Code (JESD-30) β€” S-CPGA-P655
Package Equivalence Code β€” SPGA655,47X47
Package Body Material β€” CERAMIC (metal-sealed co-fired)
Speed Grade β€” -1
Propagation Delay β€” 2.5 ns (typical for -1 grade)
Peak Reflow Temperature β€” 220 C
Operating Temperature β€” -40 C to +85 C (industrial)
Mounting Type β€” Through-Hole (PGA)

Datasheets & Resources

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