EP20K400GI655-3 vs EP20K400GC655-3 Comparison
Detailed side-by-side comparison of EP20K400GI655-3 by Altera and EP20K400GC655-3 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K400GI655-3 | EP20K400GC655-3 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $55.00 | $310.00 |
| Family | APEX 20KE | APEX 20K |
| Logic Elements / Cells | 16,640 | β |
| System Gates | 400,000 (maximum) | β |
| Maximum User I/O | 502 | β |
| Dedicated Inputs | 4 | β |
| Number of Terminals | 655 | β |
| Package | 655-Pin PGA (Plastic/CPGA, square) | β |
| JESD-30 Code | S-CPGA-P655 | β |
| Package Shape | Square | β |
| Form of Terminal | PIN/PEG (through-hole) | β |
| Mounting Type | Through-Hole (Socket) | β |
| Process Technology | CMOS, 2.5V core | 0.22 um CMOS |
| Core Supply Voltage | 2.5 V | β |
| I/O Supply Voltage | 2.5 V or 3.3 V (MultiVolt I/O) | β |
| Operating Temperature | 0Β°C to 70Β°C (Industrial I grade) | -40C to +85C (industrial) |
| Speed Grade | -3 (slowest of the EP20K400 family) | -3 (slowest grade in family) |
| Configuration Modes | Passive Serial, Passive Parallel Asynchronous, JTAG | Passive Serial, Passive Parallel Sync/Async, Active Serial |
| Embedded Memory | Dual-port RAM via Embedded System Blocks (ESBs) | β |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs status] |
| Series | β | APEX-20KC |
| Manufacturer | β | Intel (formerly Altera) |
| Logic Elements | β | 16640 |
| Total RAM Bits | β | 212992 |
| Number of Gates | β | 400000 |
| Supply Voltage - Core | β | 1.71 V to 1.89 V (1.8 V nominal) |
| I/O Voltage Tolerance | β | MultiVolt I/O: 1.8 V / 2.5 V / 3.3 V / 5 V |
| Maximum Frequency | β | 167 MHz (per FPGAkey) |
| Package / Case | β | 655-BCPGA |
| Supplier Device Package | β | 655-CPGA (62.48 x 62.48 mm) |
| Propagation Delay (tPD) | β | 3.6 ns (per Microchip USA listing) |
| JTAG Support | β | IEEE 1149.1 Boundary-Scan |