EP20K400GI655-3 vs EP20K400GC655-3 तुलना
विस्तृत दोनों ओर की तुलना EP20K400GI655-3 द्वारा Altera और EP20K400GC655-3 द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP20K400GI655-3 | EP20K400GC655-3 |
|---|---|---|
| ब्रांड | Altera | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | अंतिम बार खरीदें |
| Family | APEX 20KE | APEX 20K |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 (maximum) | — |
| Maximum User I/O | 502 | — |
| Dedicated Inputs | 4 | — |
| Number of Terminals | 655 | — |
| पैकेज | 655-Pin PGA (Plastic/CPGA, square) | — |
| JESD-30 Code | S-CPGA-P655 | — |
| Package Shape | Square | — |
| Form of Terminal | PIN/PEG (through-hole) | — |
| माउंटिंग प्रकार | Through-Hole (Socket) | — |
| Process Technology | CMOS, 2.5V core | 0.22 um CMOS |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage | 2.5 V or 3.3 V (MultiVolt I/O) | — |
| ऑपरेटिंग तापमान | 0°C to 70°C (Industrial I grade) | -40C to +85C (industrial) |
| Speed Grade | -3 (slowest of the EP20K400 family) | -3 (slowest grade in family) |
| Configuration Modes | Passive Serial, Passive Parallel Asynchronous, JTAG | Passive Serial, Passive Parallel Sync/Async, Active Serial |
| Embedded Memory | Dual-port RAM via Embedded System Blocks (ESBs) | — |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs status] |
| Series | — | APEX-20KC |
| Manufacturer | — | Intel (formerly Altera) |
| Logic Elements | — | 16640 |
| Total RAM Bits | — | 212992 |
| Number of Gates | — | 400000 |
| Supply Voltage - Core | — | 1.71 V to 1.89 V (1.8 V nominal) |
| I/O Voltage Tolerance | — | MultiVolt I/O: 1.8 V / 2.5 V / 3.3 V / 5 V |
| Maximum Frequency | — | 167 MHz (per FPGAkey) |
| पैकेज / केस | — | 655-BCPGA |
| Supplier Device Package | — | 655-CPGA (62.48 x 62.48 mm) |
| Propagation Delay (tPD) | — | 3.6 ns (per Microchip USA listing) |
| JTAG Support | — | IEEE 1149.1 Boundary-Scan |