EP20K600CB652C9 vs EP20K600CB652C-8 Comparison

Detailed side-by-side comparison of EP20K600CB652C9 by Altera and EP20K600CB652C-8 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP20K600CB652C9 EP20K600CB652C-8
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family APEX 20KC APEX 20KC (MultiCore)
Logic Elements / Cells 24,320 —
Number of LABs / CLBs 2,432 —
System Gates 1,537,000 —
Total RAM Bits 311,296 —
User I/O 488 —
Number of I/O Banks [DATA_NEEDED: I/O bank count] —
Supply Voltage 1.71 V to 1.89 V —
Process Technology 0.15 µm all-layer copper CMOS —
Internal Datapath Frequency up to 250 MHz —
Propagation Delay (typ.) 1.48 ns —
Operating Temperature 0 °C to 85 °C (commercial) 0 C to 85 C (commercial)
Package 652-BGA (45 × 45 mm, 1.27 mm pitch) 652-BGA (LBGA, 45 x 45 mm, 1.27 mm pitch)
Mounting Type Surface Mount (BGA) Surface Mount (thermally enhanced)
Configuration JTAG IEEE 1149.1 / serial / EPC2-compatible Enhanced (EPC) bitstream
RoHS Status Compliant (per Altera product page) —
Product Status Obsolete (per distributor listings) —
Series — APEX 20KC
Typical Gates — 600,000
Logic Elements — 24,320
Embedded RAM — 311,296 bits
User I/Os — 488
Propagation Delay — 1.48 ns (per published source)
Speed Grade — -8 (slowest, most timing margin)
VCCIO Options — 1.8 V / 2.5 V / 3.3 V
Process — 0.15 µm all-layer copper metal
PCI Compliance — PCI Local Bus Rev 2.2 at 33/66 MHz, 32/64-bit
Memory Interface Support — DDR SDRAM, ZBT SRAM, QDR SRAM, LVDS

Datasheets & Resources

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