EP20K600CF672C-7ES vs EP20K600CF672C-8 Comparison
Detailed side-by-side comparison of EP20K600CF672C-7ES by Altera and EP20K600CF672C-8 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K600CF672C-8 - APEX 20KC FPGA 600K Gates 24320 LEs 672-BGA | Intel / Altera
EP20K600CF672C-8 ObsoleteSpecification Comparison
| Parameter | EP20K600CF672C-7ES | EP20K600CF672C-8 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $2,050.00 | $1,150.00 |
| Family | APEX 20KC | β |
| Device Type | Field Programmable Gate Array (FPGA) | FPGA (Field Programmable Gate Array) |
| Maximum System Gates | 1,560,000 (typical 600K application gates) | β |
| Typical Logic Elements | 24,320 (per APEX 20KC 600K family) | β |
| Maximum User I/O | 488 | β |
| Total I/O Lines | 504 (per Microchip USA listing) | β |
| Total Inputs | 508 | β |
| Embedded System Blocks (ESBs) | 248 | β |
| Embedded RAM | 248 Kbits (dual-port) | β |
| PLLs | 4 | β |
| Propagation Delay | 1.48 ns to 1.6 ns | β |
| Maximum Clock Frequency | 1666.6 MHz | β |
| Speed Grade | -7 | -8 |
| Process Technology | 0.15 micron all-layer copper CMOS | 0.15 micrometer all-layer copper-metal |
| Package | 672-ball FCBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch | β |
| Operating Temperature | 0 C to 85 C (Commercial) | β |
| Core Voltage | 1.8 V (typical APEX 20KC, exact value per datasheet) | β |
| Configuration Mode | EPC serial / JTAG IEEE 1149.1 | β |
| Compliance | RoHS status unknown (verify with manufacturer datasheet) | β |
| Series | β | APEX 20KC |
| Typical Gates | β | 600,000 |
| Logic Elements (LEs) | β | 24,320 |
| Embedded Memory Bits | β | 311,296 |
| Maximum User I/Os | β | 508 |
| Number of Pins | β | 672 |
| Package Type | β | 672-BGA (FineLine BGA, 1.27 mm pitch, 45 x 45 mm) |
| Propagation Delay (tPD) | β | 1.48 ns |
| Architecture | β | MultiCore (LUT logic + embedded memory) |
| Operating Temperature Range | β | 0C to +85C (commercial) |
| Supply Voltage | β | Multi-rail (core + I/O banks) |
| Configuration Method | β | Serial / parallel / JTAG |
| Pin Compatibility | β | Pin-compatible with APEX 20KE family |
| RoHS Status | β | [DATA_NEEDED: RoHS status] |