EP20K600CF672C-7ES vs EP20K600CF672C-8 Vergleich
Detaillierter Direktvergleich von EP20K600CF672C-7ES von Altera und EP20K600CF672C-8 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EP20K600CF672C-8 - APEX 20KC FPGA 600K Gates 24320 LEs 672-BGA | Intel / Altera
EP20K600CF672C-8 ObsoleteSpezifikationsvergleich
| Parameter | EP20K600CF672C-7ES | EP20K600CF672C-8 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $2.050,00 | $1.150,00 |
| Family | APEX 20KC | — |
| Device Type | Field Programmable Gate Array (FPGA) | FPGA (Field Programmable Gate Array) |
| Maximum System Gates | 1,560,000 (typical 600K application gates) | — |
| Typical Logic Elements | 24,320 (per APEX 20KC 600K family) | — |
| Maximum User I/O | 488 | — |
| Total I/O Lines | 504 (per Microchip USA listing) | — |
| Total Inputs | 508 | — |
| Embedded System Blocks (ESBs) | 248 | — |
| Embedded RAM | 248 Kbits (dual-port) | — |
| PLLs | 4 | — |
| Propagation Delay | 1.48 ns to 1.6 ns | — |
| Maximale Taktfrequenz | 1666.6 MHz | — |
| Speed Grade | -7 | -8 |
| Process Technology | 0.15 micron all-layer copper CMOS | 0.15 micrometer all-layer copper-metal |
| Gehäuse | 672-ball FCBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch | — |
| Betriebstemperatur | 0 C to 85 C (Commercial) | — |
| Core Voltage | 1.8 V (typical APEX 20KC, exact value per datasheet) | — |
| Configuration Mode | EPC serial / JTAG IEEE 1149.1 | — |
| Compliance | RoHS status unknown (verify with manufacturer datasheet) | — |
| Series | — | APEX 20KC |
| Typical Gates | — | 600,000 |
| Logic Elements (LEs) | — | 24,320 |
| Embedded Memory Bits | — | 311,296 |
| Maximum User I/Os | — | 508 |
| Anzahl der Pins | — | 672 |
| Package Type | — | 672-BGA (FineLine BGA, 1.27 mm pitch, 45 x 45 mm) |
| Propagation Delay (tPD) | — | 1.48 ns |
| Architecture | — | MultiCore (LUT logic + embedded memory) |
| Betriebstemperaturbereich | — | 0C to +85C (commercial) |
| Versorgungsspannung | — | Multi-rail (core + I/O banks) |
| Configuration Method | — | Serial / parallel / JTAG |
| Pin Compatibility | — | Pin-compatible with APEX 20KE family |
| RoHS-Status | — | [DATA_NEEDED: RoHS status] |