EP20K600CF672C-7ES vs EP20K600CF672C-8 对比

详细并排对比 EP20K600CF672C-7ES 出自 Altera 和 EP20K600CF672C-8 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP20K600CF672C-7ES EP20K600CF672C-8
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $2,050.00 $1,150.00
Family APEX 20KC —
Device Type Field Programmable Gate Array (FPGA) FPGA (Field Programmable Gate Array)
Maximum System Gates 1,560,000 (typical 600K application gates) —
Typical Logic Elements 24,320 (per APEX 20KC 600K family) —
Maximum User I/O 488 —
Total I/O Lines 504 (per Microchip USA listing) —
Total Inputs 508 —
Embedded System Blocks (ESBs) 248 —
Embedded RAM 248 Kbits (dual-port) —
PLLs 4 —
Propagation Delay 1.48 ns to 1.6 ns —
最大时钟频率 1666.6 MHz —
Speed Grade -7 -8
Process Technology 0.15 micron all-layer copper CMOS 0.15 micrometer all-layer copper-metal
封装 672-ball FCBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch —
工作温度 0 C to 85 C (Commercial) —
Core Voltage 1.8 V (typical APEX 20KC, exact value per datasheet) —
Configuration Mode EPC serial / JTAG IEEE 1149.1 —
Compliance RoHS status unknown (verify with manufacturer datasheet) —
Series — APEX 20KC
Typical Gates — 600,000
Logic Elements (LEs) — 24,320
Embedded Memory Bits — 311,296
Maximum User I/Os — 508
引脚数 — 672
Package Type — 672-BGA (FineLine BGA, 1.27 mm pitch, 45 x 45 mm)
Propagation Delay (tPD) — 1.48 ns
Architecture — MultiCore (LUT logic + embedded memory)
工作温度范围 — 0C to +85C (commercial)
电源电压 — Multi-rail (core + I/O banks)
Configuration Method — Serial / parallel / JTAG
Pin Compatibility — Pin-compatible with APEX 20KE family
RoHS 状态 — [DATA_NEEDED: RoHS status]

数据手册与资源

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