EP20K600CF672C-8 vs EP20K600CF672C6 Comparison
Detailed side-by-side comparison of EP20K600CF672C-8 by Altera and EP20K600CF672C6 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP20K600CF672C-8 - APEX 20KC FPGA 600K Gates 24320 LEs 672-BGA | Intel / Altera
EP20K600CF672C-8 Obsolete
Specification Comparison
| Parameter | EP20K600CF672C-8 | EP20K600CF672C6 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Series | APEX 20KC | — |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| Typical Gates | 600,000 | — |
| Logic Elements (LEs) | 24,320 | 24,320 |
| Embedded Memory Bits | 311,296 | — |
| Maximum User I/Os | 508 | — |
| Number of Pins | 672 | — |
| Package Type | 672-BGA (FineLine BGA, 1.27 mm pitch, 45 x 45 mm) | — |
| Speed Grade | -8 | -6 (C6) |
| Propagation Delay (tPD) | 1.48 ns | — |
| Process Technology | 0.15 micrometer all-layer copper-metal | 0.18 µm CMOS, 6 metal layers |
| Architecture | MultiCore (LUT logic + embedded memory) | — |
| Operating Temperature Range | 0C to +85C (commercial) | — |
| Supply Voltage | Multi-rail (core + I/O banks) | — |
| Configuration Method | Serial / parallel / JTAG | SRAM-based, JTAG, EPC16/EPC2 |
| Pin Compatibility | Pin-compatible with APEX 20KE family | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-RoHS (legacy process) |
| Family | — | APEX 20KC |
| Typical Gate Count | — | 600,000 gates |
| Embedded System Blocks (ESBs) | — | 160 (each 2,048 bits) |
| Maximum Embedded RAM | — | 311,296 bits (311 kbit) |
| Maximum User I/O Pins | — | 508 |
| Package | — | 672-ball FineLine BGA (CF672) |
| Package Body Size | — | 27 mm × 27 mm |
| Operating Temperature | — | 0 °C to +85 °C (commercial) |
| Core Voltage | — | 1.8 V |
| I/O Standards Supported | — | LVCMOS, LVTTL, HSTL, SSTL, GTL+ |
| Embedded PLLs | — | 4 |