EP20K600CF672C-8 vs EP20K600CF672C6 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CF672C-8 sa pamamagitan ng Altera at EP20K600CF672C6 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K600CF672C-8 EP20K600CF672C6
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Series APEX 20KC —
Device Type FPGA (Field Programmable Gate Array) —
Typical Gates 600,000 —
Logic Elements (LEs) 24,320 24,320
Embedded Memory Bits 311,296 —
Maximum User I/Os 508 —
Bilang ng Pins 672 —
Package Type 672-BGA (FineLine BGA, 1.27 mm pitch, 45 x 45 mm) —
Speed Grade -8 -6 (C6)
Propagation Delay (tPD) 1.48 ns —
Process Technology 0.15 micrometer all-layer copper-metal 0.18 µm CMOS, 6 metal layers
Architecture MultiCore (LUT logic + embedded memory) —
Hanay ng Temperature na Operasyon 0C to +85C (commercial) —
Volte ng Pagbibigay Multi-rail (core + I/O banks) —
Configuration Method Serial / parallel / JTAG SRAM-based, JTAG, EPC16/EPC2
Pin Compatibility Pin-compatible with APEX 20KE family —
Tindminan RoHS [DATA_NEEDED: RoHS status] Non-RoHS (legacy process)
Family — APEX 20KC
Typical Gate Count — 600,000 gates
Embedded System Blocks (ESBs) — 160 (each 2,048 bits)
Maximum Embedded RAM — 311,296 bits (311 kbit)
Maximum User I/O Pins — 508
Packhaging — 672-ball FineLine BGA (CF672)
Package Body Size — 27 mm × 27 mm
Temperature na Operasyon — 0 °C to +85 °C (commercial)
Core Voltage — 1.8 V
I/O Standards Supported — LVCMOS, LVTTL, HSTL, SSTL, GTL+
Embedded PLLs — 4

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