EP2A15F672C7 vs EP2A15F672C9 Comparison
Detailed side-by-side comparison of EP2A15F672C7 by Intel and EP2A15F672C9 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2A15F672C7 | EP2A15F672C9 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $98.00 | $175.00 |
| Series | APEX II (EP2A15) | β |
| Family | APEX II FPGA | β |
| Logic Elements (LE) | 16,640 | β |
| Total System Gates | 425,984 | β |
| Maximum User I/O | 492 | β |
| Embedded Memory Bits | 425,984 | β |
| Number of Macrocells / Logic Units | 16,640 | β |
| Propagation Delay (tPD) | 1.69 ns | β |
| Core Voltage | 1.5 V | β |
| Process Technology | 0.15 Β΅m all-layer copper, up to 8 metal layers | 0.15 Β΅m all-layer copper (up to 8 metal layers) |
| High-Speed I/O Standard | True-LVDS, LVPECL, PCML, HyperTransport | β |
| True-LVDS Data Rate | 1 Gbps | β |
| Package | 672-ball FineLine BGA (FCBGA) | 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine) |
| Package Dimensions | 27 mm Γ 27 mm, 1.0 mm pitch | β |
| Mounting Type | Surface Mount | β |
| Operating Temperature | Commercial (0Β°C to +85Β°C) | 0 Β°C to 85 Β°C (commercial) |
| Speed Grade | C7 | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Logic Family | β | APEX II (CMOS) |
| Usable Gates | β | 600 K |
| Logic Elements | β | 16640 |
| Macrocells | β | 1664 |
| Maximum User I/Os | β | 492 |
| Core Supply Voltage | β | 1.5 V |
| I/O Supply Voltage | β | 3.3 V |
| Maximum Internal Frequency | β | 379 MHz |
| Propagation Delay | β | 1.94 ns |
| High-Speed I/O Support | β | True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps |
| Embedded Memory | β | ESB dual-port RAM / FIFO |
| Configuration Interface | β | Passive serial / Active serial / JTAG (IEEE 1149.1) |
| PLLs | β | On-chip PLLs for clock synthesis and deskew |
| Compliance | β | RoHS - [DATA_NEEDED: status not in verified data]; IEEE 1149.1 boundary scan |