EP2A15F672C7 vs EP2A15F672C9 Comparaison
Comparaison détaillée côte à côte de EP2A15F672C7 par Intel et EP2A15F672C9 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2A15F672C7 | EP2A15F672C9 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $98,00 | $175,00 |
| Series | APEX II (EP2A15) | — |
| Family | APEX II FPGA | — |
| Logic Elements (LE) | 16,640 | — |
| Total System Gates | 425,984 | — |
| Maximum User I/O | 492 | — |
| Embedded Memory Bits | 425,984 | — |
| Number of Macrocells / Logic Units | 16,640 | — |
| Propagation Delay (tPD) | 1.69 ns | — |
| Core Voltage | 1.5 V | — |
| Process Technology | 0.15 µm all-layer copper, up to 8 metal layers | 0.15 µm all-layer copper (up to 8 metal layers) |
| High-Speed I/O Standard | True-LVDS, LVPECL, PCML, HyperTransport | — |
| True-LVDS Data Rate | 1 Gbps | — |
| Boîtier | 672-ball FineLine BGA (FCBGA) | 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine) |
| Package Dimensions | 27 mm × 27 mm, 1.0 mm pitch | — |
| Type de montage | Surface Mount | — |
| Température de fonctionnement | Commercial (0°C to +85°C) | 0 °C to 85 °C (commercial) |
| Speed Grade | C7 | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | — |
| Logic Family | — | APEX II (CMOS) |
| Usable Gates | — | 600 K |
| Logic Elements | — | 16640 |
| Macrocells | — | 1664 |
| Maximum User I/Os | — | 492 |
| Core Supply Voltage | — | 1.5 V |
| I/O Supply Voltage | — | 3.3 V |
| Maximum Internal Frequency | — | 379 MHz |
| Propagation Delay | — | 1.94 ns |
| High-Speed I/O Support | — | True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps |
| Embedded Memory | — | ESB dual-port RAM / FIFO |
| Configuration Interface | — | Passive serial / Active serial / JTAG (IEEE 1149.1) |
| PLLs | — | On-chip PLLs for clock synthesis and deskew |
| Compliance | — | RoHS - [DATA_NEEDED: status not in verified data]; IEEE 1149.1 boundary scan |