EP2A15F672C7 vs EP2A15F672C9 对比

详细并排对比 EP2A15F672C7 出自 Intel 和 EP2A15F672C9 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP2A15F672C7 EP2A15F672C9
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $98.00 $175.00
Series APEX II (EP2A15) —
Family APEX II FPGA —
Logic Elements (LE) 16,640 —
Total System Gates 425,984 —
Maximum User I/O 492 —
Embedded Memory Bits 425,984 —
Number of Macrocells / Logic Units 16,640 —
Propagation Delay (tPD) 1.69 ns —
Core Voltage 1.5 V —
Process Technology 0.15 µm all-layer copper, up to 8 metal layers 0.15 µm all-layer copper (up to 8 metal layers)
High-Speed I/O Standard True-LVDS, LVPECL, PCML, HyperTransport —
True-LVDS Data Rate 1 Gbps —
封装 672-ball FineLine BGA (FCBGA) 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine)
Package Dimensions 27 mm × 27 mm, 1.0 mm pitch —
安装类型 Surface Mount —
工作温度 Commercial (0°C to +85°C) 0 °C to 85 °C (commercial)
Speed Grade C7 —
RoHS 状态 [DATA_NEEDED: RoHS status] —
Logic Family — APEX II (CMOS)
Usable Gates — 600 K
Logic Elements — 16640
Macrocells — 1664
Maximum User I/Os — 492
Core Supply Voltage — 1.5 V
I/O Supply Voltage — 3.3 V
Maximum Internal Frequency — 379 MHz
Propagation Delay — 1.94 ns
High-Speed I/O Support — True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps
Embedded Memory — ESB dual-port RAM / FIFO
Configuration Interface — Passive serial / Active serial / JTAG (IEEE 1149.1)
PLLs — On-chip PLLs for clock synthesis and deskew
Compliance — RoHS - [DATA_NEEDED: status not in verified data]; IEEE 1149.1 boundary scan

数据手册与资源

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