EP2A15F672C9 vs EP2A15F672I8 Comparison

Detailed side-by-side comparison of EP2A15F672C9 by Altera and EP2A15F672I8 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EP2A15F672C9

EP2A15F672C9 - 16,640-Cell APEX II FPGA, 672-FBGA | Intel / Altera

EP2A15F672C9 Obsolete
Altera
EP2A15F672I8

EP2A15F672I8 - APEX II 600K Gate FPGA, 672-FBGA | Altera

EP2A15F672I8 ⚠ Last Time Buy

Specification Comparison

Parameter EP2A15F672C9 EP2A15F672I8
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $175.00 $680.00
Logic Family APEX II (CMOS) β€”
Usable Gates 600 K β€”
Logic Elements 16640 β€”
Macrocells 1664 β€”
Maximum User I/Os 492 β€”
Package 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine) 672-FBGA, FCBGA, 27 x 27 mm, 1.0 mm pitch
Process Technology 0.15 Β΅m all-layer copper (up to 8 metal layers) 0.15 Β΅m all-layer copper CMOS
Core Supply Voltage 1.5 V 1.5 V (1.425 V – 1.575 V)
I/O Supply Voltage 3.3 V β€”
Maximum Internal Frequency 379 MHz 435 MHz
Propagation Delay 1.94 ns β€”
High-Speed I/O Support True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps β€”
Embedded Memory ESB dual-port RAM / FIFO 416 Kbits
Operating Temperature 0 Β°C to 85 Β°C (commercial) -40 Β°C to +100 Β°C (TJ, industrial)
Configuration Interface Passive serial / Active serial / JTAG (IEEE 1149.1) β€”
PLLs On-chip PLLs for clock synthesis and deskew β€”
Compliance RoHS - [DATA_NEEDED: status not in verified data]; IEEE 1149.1 boundary scan β€”
Family β€” APEX II
Metal Layers β€” Up to 8
Typical Gates β€” 600 K
Logic Elements / Cells β€” 16,640
User I/Os β€” 492
Propagation Delay (typ.) β€” 1.94 ns
Supply Voltage Range β€” 1.425 V to 1.575 V
Mounting Type β€” Surface Mount (BGA)
I/O Standards β€” LVTTL, LVCMOS, LVDS, MultiVolt I/O
RoHS Status β€” [DATA_NEEDED: RoHS status]

Datasheets & Resources

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