EP2A15F672C9 vs EP2A15F672I8 对比
详细并排对比 EP2A15F672C9 出自 Altera 和 EP2A15F672I8 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP2A15F672C9 | EP2A15F672I8 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 最后采购期 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $175.00 | $680.00 |
| Logic Family | APEX II (CMOS) | — |
| Usable Gates | 600 K | — |
| Logic Elements | 16640 | — |
| Macrocells | 1664 | — |
| Maximum User I/Os | 492 | — |
| 封装 | 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine) | 672-FBGA, FCBGA, 27 x 27 mm, 1.0 mm pitch |
| Process Technology | 0.15 µm all-layer copper (up to 8 metal layers) | 0.15 µm all-layer copper CMOS |
| Core Supply Voltage | 1.5 V | 1.5 V (1.425 V – 1.575 V) |
| I/O Supply Voltage | 3.3 V | — |
| Maximum Internal Frequency | 379 MHz | 435 MHz |
| Propagation Delay | 1.94 ns | — |
| High-Speed I/O Support | True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps | — |
| Embedded Memory | ESB dual-port RAM / FIFO | 416 Kbits |
| 工作温度 | 0 °C to 85 °C (commercial) | -40 °C to +100 °C (TJ, industrial) |
| Configuration Interface | Passive serial / Active serial / JTAG (IEEE 1149.1) | — |
| PLLs | On-chip PLLs for clock synthesis and deskew | — |
| Compliance | RoHS - [DATA_NEEDED: status not in verified data]; IEEE 1149.1 boundary scan | — |
| Family | — | APEX II |
| Metal Layers | — | Up to 8 |
| Typical Gates | — | 600 K |
| Logic Elements / Cells | — | 16,640 |
| User I/Os | — | 492 |
| Propagation Delay (typ.) | — | 1.94 ns |
| Supply Voltage Range | — | 1.425 V to 1.575 V |
| 安装类型 | — | Surface Mount (BGA) |
| I/O Standards | — | LVTTL, LVCMOS, LVDS, MultiVolt I/O |
| RoHS 状态 | — | [DATA_NEEDED: RoHS status] |