EP2A15F672C9 vs EP2A15F672I8 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A15F672C9 sa pamamagitan ng Altera at EP2A15F672I8 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2A15F672C9 | EP2A15F672I8 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Logic Family | APEX II (CMOS) | — |
| Usable Gates | 600 K | — |
| Logic Elements | 16640 | — |
| Macrocells | 1664 | — |
| Maximum User I/Os | 492 | — |
| Packhaging | 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine) | 672-FBGA, FCBGA, 27 x 27 mm, 1.0 mm pitch |
| Process Technology | 0.15 µm all-layer copper (up to 8 metal layers) | 0.15 µm all-layer copper CMOS |
| Core Supply Voltage | 1.5 V | 1.5 V (1.425 V – 1.575 V) |
| I/O Supply Voltage | 3.3 V | — |
| Maximum Internal Frequency | 379 MHz | 435 MHz |
| Propagation Delay | 1.94 ns | — |
| High-Speed I/O Support | True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps | — |
| Embedded Memory | ESB dual-port RAM / FIFO | 416 Kbits |
| Temperature na Operasyon | 0 °C to 85 °C (commercial) | -40 °C to +100 °C (TJ, industrial) |
| Configuration Interface | Passive serial / Active serial / JTAG (IEEE 1149.1) | — |
| PLLs | On-chip PLLs for clock synthesis and deskew | — |
| Compliance | RoHS - [DATA_NEEDED: status not in verified data]; IEEE 1149.1 boundary scan | — |
| Family | — | APEX II |
| Metal Layers | — | Up to 8 |
| Typical Gates | — | 600 K |
| Logic Elements / Cells | — | 16,640 |
| User I/Os | — | 492 |
| Propagation Delay (typ.) | — | 1.94 ns |
| Supply Voltage Range | — | 1.425 V to 1.575 V |
| Uri ng Pagpapasok | — | Surface Mount (BGA) |
| I/O Standards | — | LVTTL, LVCMOS, LVDS, MultiVolt I/O |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |