EP2A15F672C9 vs EP2A25F672C9ES Comparison
Detailed side-by-side comparison of EP2A15F672C9 by Altera and EP2A25F672C9ES by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2A15F672C9 | EP2A25F672C9ES |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $175.00 | $122.00 |
| Logic Family | APEX II (CMOS) | CMOS |
| Usable Gates | 600 K | β |
| Logic Elements | 16640 | 24,320 |
| Macrocells | 1664 | β |
| Maximum User I/Os | 492 | β |
| Package | 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine) | 672-pin FC-FBGA (FineLine BGA), 27 x 27 mm, 1.0 mm pitch |
| Process Technology | 0.15 Β΅m all-layer copper (up to 8 metal layers) | 0.15 Β΅m CMOS (up to 8 metal layers, all-layer copper) |
| Core Supply Voltage | 1.5 V | 1.5 V |
| I/O Supply Voltage | 3.3 V | β |
| Maximum Internal Frequency | 379 MHz | β |
| Propagation Delay | 1.94 ns | 1.69 ns |
| High-Speed I/O Support | True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps | β |
| Embedded Memory | ESB dual-port RAM / FIFO | β |
| Operating Temperature | 0 Β°C to 85 Β°C (commercial) | 0 Β°C to 85 Β°C (Commercial) |
| Configuration Interface | Passive serial / Active serial / JTAG (IEEE 1149.1) | β |
| PLLs | On-chip PLLs for clock synthesis and deskew | β |
| Compliance | RoHS - [DATA_NEEDED: status not in verified data]; IEEE 1149.1 boundary scan | β |
| Family | β | APEX II |
| System Gates | β | 900,000 |
| Maximum Operating Frequency | β | 236 MHz |
| User I/Os | β | 492 |
| Speed Grade | β | -9 |
| Configuration Class | β | ES (Enhanced) |
| Mounting Type | β | Surface Mount |
| RoHS Status | β | [DATA_NEEDED: RoHS compliance status] |
| MSL Level | β | [DATA_NEEDED: MSL moisture sensitivity level] |