EP2A15F672C9 vs EP2A25F672C9ES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A15F672C9 sa pamamagitan ng Altera at EP2A25F672C9ES sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2A15F672C9 | EP2A25F672C9ES |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Logic Family | APEX II (CMOS) | CMOS |
| Usable Gates | 600 K | — |
| Logic Elements | 16640 | 24,320 |
| Macrocells | 1664 | — |
| Maximum User I/Os | 492 | — |
| Packhaging | 672-ball FC-FBGA (27 x 27 mm, 1 mm pitch, FineLine) | 672-pin FC-FBGA (FineLine BGA), 27 x 27 mm, 1.0 mm pitch |
| Process Technology | 0.15 µm all-layer copper (up to 8 metal layers) | 0.15 µm CMOS (up to 8 metal layers, all-layer copper) |
| Core Supply Voltage | 1.5 V | 1.5 V |
| I/O Supply Voltage | 3.3 V | — |
| Maximum Internal Frequency | 379 MHz | — |
| Propagation Delay | 1.94 ns | 1.69 ns |
| High-Speed I/O Support | True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps | — |
| Embedded Memory | ESB dual-port RAM / FIFO | — |
| Temperature na Operasyon | 0 °C to 85 °C (commercial) | 0 °C to 85 °C (Commercial) |
| Configuration Interface | Passive serial / Active serial / JTAG (IEEE 1149.1) | — |
| PLLs | On-chip PLLs for clock synthesis and deskew | — |
| Compliance | RoHS - [DATA_NEEDED: status not in verified data]; IEEE 1149.1 boundary scan | — |
| Family | — | APEX II |
| System Gates | — | 900,000 |
| Maximum Operating Frequency | — | 236 MHz |
| User I/Os | — | 492 |
| Speed Grade | — | -9 |
| Configuration Class | — | ES (Enhanced) |
| Uri ng Pagpapasok | — | Surface Mount |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS compliance status] |
| Level ng MSL | — | [DATA_NEEDED: MSL moisture sensitivity level] |