EP2A25F672C9N vs EP2A25F672I6 Comparison
Detailed side-by-side comparison of EP2A25F672C9N by Intel and EP2A25F672I6 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2A25F672C9N | EP2A25F672I6 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $195.00 | $178.00 |
| Family | APEX II | APEX II |
| Logic Elements / Cells | 24320 | β |
| System Gates | Approx. 900000 | β |
| Maximum User I/O | 492 | β |
| Operating Frequency | 236 MHz | β |
| Core Supply Voltage (VCCINT) | 1.425 V to 1.575 V (nominal 1.5 V) | β |
| Process Technology | 0.15 Β΅m all-layer copper, up to 8 metal layers | 0.18 Β΅m CMOS |
| Package | 672-ball FineLine BGA (F672), 27 Γ 27 mm, 1.00 mm pitch | 672-ball FineLine BGA (FBGA-672) |
| Mounting Type | Surface Mount (BGA) | Surface Mount (BGA) |
| Seated Height (max) | 2.100 mm | β |
| Propagation Delay | 2.23 ns | β |
| Logic Family | CMOS | β |
| Operating Temperature | 0 Β°C to +85 Β°C (commercial, C9 grade) | β |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, LVDS, LVPECL, PCML, HyperTransport | β |
| LVDS Data Rate | Up to 1 Gbps (True-LVDS) | β |
| Configuration Interface | Serial / Parallel PROM, JTAG, passive parallel (enhanced) | β |
| Embedded Memory | Enhanced System Blocks (ESBs) for dual-port RAM | Embedded System Blocks (ESB), dual-port RAM / CAM |
| Design Software | Quartus II (v5.1 or later) | β |
| RoHS Status | Compliant (per distributor listings) | [DATA_NEEDED: RoHS compliance status] |
| Logic Elements (typical gates) | β | 25,000 |
| Fabric Architecture | β | SRAM-based LUT |
| Core Voltage | β | 1.5 V |
| Configuration Method | β | External SRAM configuration device (EPC series) |
| Temperature Grade | β | Industrial (-40 Β°C to +100 Β°C ambient) |
| Speed Grade | β | 6 |
| DSP Blocks | β | MultiCore dedicated multipliers |
| Boundary Scan | β | JTAG (IEEE 1149.1) compliant |
| Clock Management | β | Dedicated PLL / clock tree circuitry |
| I/O Bank Count | β | [DATA_NEEDED: number of user I/O banks] |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |
| MSL Level | β | [DATA_NEEDED: moisture sensitivity level] |