EP2A25F672C9N vs EP2A25F672I6 Perbandingan
Perbandingan bersamaan detil EP2A25F672C9N dari Intel dan EP2A25F672I6 dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP2A25F672C9N | EP2A25F672I6 |
|---|---|---|
| Merek | Intel | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Family | APEX II | APEX II |
| Logic Elements / Cells | 24320 | — |
| System Gates | Approx. 900000 | — |
| Maximum User I/O | 492 | — |
| Operating Frequency | 236 MHz | — |
| Core Supply Voltage (VCCINT) | 1.425 V to 1.575 V (nominal 1.5 V) | — |
| Process Technology | 0.15 µm all-layer copper, up to 8 metal layers | 0.18 µm CMOS |
| Paket | 672-ball FineLine BGA (F672), 27 × 27 mm, 1.00 mm pitch | 672-ball FineLine BGA (FBGA-672) |
| Tipe Mounting | Surface Mount (BGA) | Surface Mount (BGA) |
| Seated Height (max) | 2.100 mm | — |
| Propagation Delay | 2.23 ns | — |
| Logic Family | CMOS | — |
| Suhu Kerja | 0 °C to +85 °C (commercial, C9 grade) | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, LVDS, LVPECL, PCML, HyperTransport | — |
| LVDS Data Rate | Up to 1 Gbps (True-LVDS) | — |
| Configuration Interface | Serial / Parallel PROM, JTAG, passive parallel (enhanced) | — |
| Embedded Memory | Enhanced System Blocks (ESBs) for dual-port RAM | Embedded System Blocks (ESB), dual-port RAM / CAM |
| Design Software | Quartus II (v5.1 or later) | — |
| Status RoHS | Compliant (per distributor listings) | [DATA_NEEDED: RoHS compliance status] |
| Logic Elements (typical gates) | — | 25,000 |
| Fabric Architecture | — | SRAM-based LUT |
| Core Voltage | — | 1.5 V |
| Configuration Method | — | External SRAM configuration device (EPC series) |
| Temperature Grade | — | Industrial (-40 °C to +100 °C ambient) |
| Speed Grade | — | 6 |
| DSP Blocks | — | MultiCore dedicated multipliers |
| Boundary Scan | — | JTAG (IEEE 1149.1) compliant |
| Clock Management | — | Dedicated PLL / clock tree circuitry |
| I/O Bank Count | — | [DATA_NEEDED: number of user I/O banks] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Level MSL | — | [DATA_NEEDED: moisture sensitivity level] |