EP2A25F672I-7 vs EP2A25F672I-9 Comparison
Detailed side-by-side comparison of EP2A25F672I-7 by Intel and EP2A25F672I-9 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP2A25F672I-9
EP2A25F672I-9 - APEX II 25K LUT FPGA, 672-BGA | Intel / Altera
EP2A25F672I-9 ObsoleteSpecification Comparison
| Parameter | EP2A25F672I-7 | EP2A25F672I-9 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $171.00 | $195.00 |
| Family | APEX II | APEX II |
| Manufacturer | Intel (formerly Altera) | β |
| Device Type | FPGA (Field-Programmable Gate Array) | β |
| System Gates | 900K (approximately) | β |
| Logic Cells / Elements | 24,320 | β |
| Maximum Operating Frequency | 500 MHz | β |
| Process Technology | 0.15 um | 0.18 Β΅m CMOS |
| Core Voltage | 1.5 V | 1.5 V / 1.8 V (speed-grade dependent) |
| Package | 672-pin FC-FBGA | 672-pin FCBGA (FineLine BGA) |
| Mounting Type | Surface Mount (Flip-Chip BGA) | Surface Mount (BGA) |
| Speed Grade | -7 | -9 |
| Operating Temperature | -40C to +85C (Industrial) | β |
| Temperature Grade | Industrial (I) | β |
| Configuration Method | JTAG, Passive Serial, Active Serial | JTAG / serial configuration EPROM |
| JTAG Support | IEEE 1149.1 Boundary Scan | β |
| RoHS Status | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status] |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Embedded Memory | ESBs (Embedded System Blocks) | β |
| Logic Elements (typical) | β | 25,000 |
| Maximum System Gates | β | [DATA_NEEDED: maximum system gates] |
| Embedded System Blocks (ESB) Memory | β | 1,125 Kbits |
| Maximum User I/O Pins | β | [DATA_NEEDED: maximum user I/O pins] |
| Number of PLLs | β | 4 |
| Operating Temperature Grade | β | Industrial (-40 Β°C to +100 Β°C junction) |
| Moisture Sensitivity Level (MSL) | β | 3 (per Vyrian listing) |
| Peak Reflow Temperature | β | 220 Β°C (per Vyrian listing) |
| Supported I/O Standards | β | LVTTL, LVCMOS, LVDS, PCI |
| Legacy Status | β | Obsolete - consult Altera / Intel FPGA archive for documentation |