EP2A25F672I-7 vs EP2A25F672I-9 Comparaison
Comparaison détaillée côte à côte de EP2A25F672I-7 par Intel et EP2A25F672I-9 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2A25F672I-7 | EP2A25F672I-9 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $171,00 | $195,00 |
| Family | APEX II | APEX II |
| Manufacturer | Intel (formerly Altera) | — |
| Device Type | FPGA (Field-Programmable Gate Array) | — |
| System Gates | 900K (approximately) | — |
| Logic Cells / Elements | 24,320 | — |
| Maximum Operating Frequency | 500 MHz | — |
| Process Technology | 0.15 um | 0.18 µm CMOS |
| Core Voltage | 1.5 V | 1.5 V / 1.8 V (speed-grade dependent) |
| Boîtier | 672-pin FC-FBGA | 672-pin FCBGA (FineLine BGA) |
| Type de montage | Surface Mount (Flip-Chip BGA) | Surface Mount (BGA) |
| Speed Grade | -7 | -9 |
| Température de fonctionnement | -40C to +85C (Industrial) | — |
| Temperature Grade | Industrial (I) | — |
| Configuration Method | JTAG, Passive Serial, Active Serial | JTAG / serial configuration EPROM |
| JTAG Support | IEEE 1149.1 Boundary Scan | — |
| Statut RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status] |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Embedded Memory | ESBs (Embedded System Blocks) | — |
| Logic Elements (typical) | — | 25,000 |
| Maximum System Gates | — | [DATA_NEEDED: maximum system gates] |
| Embedded System Blocks (ESB) Memory | — | 1,125 Kbits |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O pins] |
| Number of PLLs | — | 4 |
| Operating Temperature Grade | — | Industrial (-40 °C to +100 °C junction) |
| Niveau de sensibilité à l'humidité (MSL) | — | 3 (per Vyrian listing) |
| Peak Reflow Temperature | — | 220 °C (per Vyrian listing) |
| Supported I/O Standards | — | LVTTL, LVCMOS, LVDS, PCI |
| Legacy Status | — | Obsolete - consult Altera / Intel FPGA archive for documentation |