EP2A25F672I-9 vs EP2A25F672I7N Comparison
Detailed side-by-side comparison of EP2A25F672I-9 by Intel and EP2A25F672I7N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2A25F672I-9 | EP2A25F672I7N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | APEX II | APEX II |
| Logic Elements (typical) | 25,000 | — |
| Maximum System Gates | [DATA_NEEDED: maximum system gates] | — |
| Embedded System Blocks (ESB) Memory | 1,125 Kbits | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O pins] | — |
| Number of PLLs | 4 | — |
| Process Technology | 0.18 µm CMOS | 0.15 µm CMOS |
| Core Voltage | 1.5 V / 1.8 V (speed-grade dependent) | — |
| Operating Temperature Grade | Industrial (-40 °C to +100 °C junction) | Industrial (I) |
| Speed Grade | -9 | 7 |
| Package | 672-pin FCBGA (FineLine BGA) | 672-ball FC-FBGA |
| Mounting Type | Surface Mount (BGA) | Surface Mount (BGA) |
| Moisture Sensitivity Level (MSL) | 3 (per Vyrian listing) | — |
| Peak Reflow Temperature | 220 °C (per Vyrian listing) | — |
| Configuration Method | JTAG / serial configuration EPROM | — |
| Supported I/O Standards | LVTTL, LVCMOS, LVDS, PCI | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Legacy Status | Obsolete - consult Altera / Intel FPGA archive for documentation | — |
| Logic Elements (Cells) | — | 24,320 |
| Typical Gate Count | — | 900,000 |
| Maximum Internal Frequency | — | 500 MHz |
| Core Supply Voltage | — | 1.5 V |
| Pin/Ball Count | — | 672 |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Fast Passive Parallel |
| Design Software | — | Quartus II |
| Lifecycle Status | — | Not Recommended for New Designs (NRND) |