EP2A25F672I-9 vs EP2A25F672I7N 比較
詳細並排比較 EP2A25F672I-9 由 Intel 與 EP2A25F672I7N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2A25F672I-9 | EP2A25F672I7N |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | APEX II | APEX II |
| Logic Elements (typical) | 25,000 | — |
| Maximum System Gates | [DATA_NEEDED: maximum system gates] | — |
| Embedded System Blocks (ESB) Memory | 1,125 Kbits | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O pins] | — |
| Number of PLLs | 4 | — |
| Process Technology | 0.18 µm CMOS | 0.15 µm CMOS |
| Core Voltage | 1.5 V / 1.8 V (speed-grade dependent) | — |
| Operating Temperature Grade | Industrial (-40 °C to +100 °C junction) | Industrial (I) |
| Speed Grade | -9 | 7 |
| 封裝 | 672-pin FCBGA (FineLine BGA) | 672-ball FC-FBGA |
| 安裝類型 | Surface Mount (BGA) | Surface Mount (BGA) |
| 濕度敏感等級 (MSL) | 3 (per Vyrian listing) | — |
| Peak Reflow Temperature | 220 °C (per Vyrian listing) | — |
| Configuration Method | JTAG / serial configuration EPROM | — |
| Supported I/O Standards | LVTTL, LVCMOS, LVDS, PCI | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Legacy Status | Obsolete - consult Altera / Intel FPGA archive for documentation | — |
| Logic Elements (Cells) | — | 24,320 |
| Typical Gate Count | — | 900,000 |
| Maximum Internal Frequency | — | 500 MHz |
| Core Supply Voltage | — | 1.5 V |
| Pin/Ball Count | — | 672 |
| Configuration Interface | — | JTAG (IEEE 1149.1), Passive Serial, Fast Passive Parallel |
| Design Software | — | Quartus II |
| 生命週期狀態 | — | Not Recommended for New Designs (NRND) |